LMK04828SNKDREP datasheet(13/102 Pages) TI

13 / 102 page

SDIO

(WRITE)

SCLK

CS*

tcH

tcS

tdS

tSCLK

tHIGH

tLOW

tdH

SDIO

(Read)

R/W

tdV

Data valid only

during read

A12 to A0,

D7 to D2

D7 to

LMK04828-EP

www.ti.com

SNAS703 – APRIL 2017

Product Folder Links: LMK04828-EP

Submit Documentation Feedback

(1)

20 MHz

7.6 SPI Interface Timing

MIN

NOM

MAX

UNIT

tds

Setup time for SDI edge to SCLK rising edge

See Figure 1

tdH

Hold time for SDI edge from SCLK rising edge

See Figure 1

tSCLK

Period of SCLK

See Figure 1

50(1)

tHIGH

High width of SCLK

See Figure 1

tLOW

Low width of SCLK

See Figure 1

tcs

Setup time for CS* falling edge to SCLK rising

edge

See Figure 1

tcH

Hold time for CS* rising edge from SCLK rising

edge

See Figure 1

tdv

SCLK falling edge to valid read back data

See Figure 1

7.7 Timing Diagram

signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed.

A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal

should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is

sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this

programming.

4-wire mode read back has the same timing as the SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 is written as 0.

Figure 1. SPI Timing Diagram

LMK04828SNKDREP Datasheet(PDF) 13 Page - Texas Instruments

LMK04828SNKDREP Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL