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LMK04828SNKDREP Datasheet(PDF) 60 Page - Texas Instruments

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Part # LMK04828SNKDREP
Description  LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LMK04828SNKDREP Datasheet(HTML) 60 Page - Texas Instruments

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LMK04828-EP
SNAS703 – APRIL 2017
www.ti.com
Product Folder Links: LMK04828-EP
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Copyright © 2017, Texas Instruments Incorporated
9.7.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE
This register has CLKin_SEL1 controls and register readback SDIO pin type.
Table 40. Register 0x149
BIT
NAME
POR
DEFAULT
DESCRIPTION
7
NA
0
Reserved
6
SDIO_RDBK_TYPE
1
Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.
0: Output, push-pull
1: Output, open drain.
5:3
CLKin_SEL1_MUX
0
This set the output value of the CLKin_SEL1 pin. This register only applies if
CLKin_SEL1_TYPE is set to an output mode.
Field Value
Output Format
0 (0x00)
Logic Low
1 (0x01)
CLKin1 LOS
2 (0x02)
CLKin1 Selected
3 (0x03)
DAC Locked
4 (0x04)
DAC Low
5 (0x05)
DAC High
6 (0x06)
SPI Readback
7 (0x07)
Reserved
2:0
CLKin_SEL1_TYPE
2
This sets the IO type of the CLKin_SEL1 pin.
Field Value
Configuration
Function
0 (0x00)
Input
Input mode, see Input Clock
Switching - Pin Select Mode for
description of input mode.
1 (0x01)
Input /w pull-up resistor
2 (0x02)
Input /w pull-down resistor
3 (0x03)
Output (push-pull)
Output modes; see the
CLKin_SEL1_MUX register for
description of outputs.
4 (0x04)
Output inverted (push-pull)
5 (0x05)
Reserved
6 (0x06)
Output (open drain)



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