LMK04828SNKDREP datasheet(1/102 Pages) TI

Part #	LMK04828SNKDREP

Description	LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

PDF	102 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

Logo

1 / 102 page

DAC

Recovered

³GLUW\´ FORFN RU

clean clock

0XOWLSOH ³FOHDQ´

clocks at different

frequencies

DCLKout0 &

DCLKout2

DCLKout12

DCLKout4,

SDCLKout5

FPGA

CLKin0

Crystal or

VCXO

Backup

Reference

Clock

CLKin1

OSCout

DAC

SDCLKout1 &

SDCLKout3

ADC

LMX2582

PLL+VCO

Serializer/

Deserializer

LMK04828-EP

SDCLKout13

SDCLKout9 &

SDCLKout11

DCLKout8 &

DCLKout10

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMK04828-EP

SNAS703 – APRIL 2017

LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

1

1 Features

1

•

EP Features

–

Gold Bondwires

–

Temperature Range: –55 to +105 °C

–

Lead Finish SnPb

•

Maximum Distribution Frequency: 3.2 GHz

•

JESD204B Support

•

Ultra-Low RMS Jitter

–

88-fs RMS Jitter (12 kHz to 20 MHz)

–

91-fs RMS Jitter (100 Hz to 20 MHz)

–

–162.5 dBc/Hz Noise Floor at 245.76 MHz

•

Up to 14 Differential Device Clocks From PLL2

–

Up to 7 SYSREF Clocks

–

Maximum Clock Output Frequency 3.2 GHz

–

LVPECL, LVDS, HSDS, LCPECL

Programmable Outputs From PLL2

•

Up to 1 Buffered VCXO/Crystal Output From PLL1

–

LVPECL, LVDS, 2xLVCMOS Programmable

•

Multi-Mode: Dual PLL, Single PLL, and Clock

Distribution

•

Dual Loop PLLatinum™ PLL Architecture

•

PLL1

–

Up to 3 Redundant Input Clocks

–

Automatic and Manual Switchover Modes

–

Hitless Switching and LOS

–

Integrated Low-Noise Crystal Oscillator Circuit

–

Holdover Mode When Input Clocks are Lost

•

PLL2

–

Normalized [1 Hz] PLL Noise Floor of

–227 dBc/Hz

–

Phase Detector Rate up to 155 MHz

–

OSCin Frequency-Doubler

–

Two Integrated Low-Noise VCOs

•

50% Duty Cycle Output Divides, 1 to 32

(Even and Odd)

•

Precision Digital Delay, Dynamically Adjustable

•

25-ps Step Analog Delay

•

3.15-V to 3.45-V Operation

•

Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8

mm)

2 Applications

•

Wireless Infrastructure

•

Data Converter Clocking

•

Networking, SONET/SDH, DSLAM

•

Medical / Video / Military / Aerospace

•

Test and Measurement

3 Description

The LMK04828-EP device is the industry's highest

performance

clock

conditioner

with

JESD204B

support.

The 14 clock outputs from PLL2 can be configured to

drive seven JESD204B converters or other logic

devices using device and SYSREF clocks. SYSREF

can be provided using both DC and AC coupling. Not

limited to JESD204B applications, each of the 14

outputs can be individually configured as high-

performance outputs for traditional clocking systems.

The high performance combined with features like the

ability to trade off between power or performance,

dual VCOs, dynamic digital delay, holdover, and

glitchless analog delay make the LMK04828-EP ideal

for providing flexible high-performance clocking trees.

Device Information(1)

PART

NUMBER

VCO0

FREQUENCY

VCO1 FREQUENCY

LMK04828-EP

2450 to 2755 MHz

2875 to 3080 MHz

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic

Similar Part No. - LMK04828SNKDREP

Manufacturer	Part #	Datasheet	Description
Texas Instruments	LMK04828SNKDREP	2Mb / 102P	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner
Texas Instruments	LMK04828SNKDREP	2Mb / 102P	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner

More results

Similar Description - LMK04828SNKDREP

Manufacturer	Part #	Datasheet	Description
Texas Instruments	LMK04826B	2Mb / 101P	LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
	LMK04826B	2Mb / 104P	Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs
	LMK04821	2Mb / 113P	Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
	LMK04610	1Mb / 124P	Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
	LMK04616	1Mb / 128P	Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
	LMK04828-EP	2Mb / 102P	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner
	LMK04832	386Kb / 8P	LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
	LMK04828-EP	2Mb / 102P	Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner
	LMK04228	1Mb / 91P	LMK04228 Ultra-Low Noise, JESD204B-Compliant Clock Jitter Cleaner With Dual-Loop PLLs
	LMK04368-EP	2Mb / 110P	LMK04368-EP Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner MAY 2023

More results

LMK04828SNKDREP Datasheet(PDF) 1 Page - Texas Instruments

LMK04828SNKDREP Datasheet(HTML) 1 Page - Texas Instruments

Similar Part No. - LMK04828SNKDREP

Similar Description - LMK04828SNKDREP

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL