CS42L56 datasheet(49/92 Pages) CIRRUS

49 / 92 page

DS851F2

CS42L56

4.9

Digital Interface Format

The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit depths from

16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 32-33 illustrate

the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 23 for exact

timing relationship between clocks and data.

For additional information, application note AN282 presents a tutorial of the 2-channel serial audio interface.

AN282 can be downloaded from the Cirrus Logic web site at http://www.cirrus.com.

4.10 Initialization

The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, del-

ta-sigma modulators and control port registers are reset. The charge pump, LDO, internal voltage reference

and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state

until the RESET pin is brought high. The control port is accessible once RESET is high and the desired reg-

ister settings can be loaded per the interface descriptions in the “Register Description” on page 58.

After the PDN bit is released and MCLK is valid, the quiescent voltage, VQ, and the internal voltage refer-

ence, FILT+, will begin powering up to normal operation. The charge pump slowly powers up and charges

the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-

alog/digital outputs enter a muted state. MCLK occurrences are counted over one LRCK period to determine

a valid MCLK/LRCK ratio and normal operation begins.

4.11 Recommended DAC to HP or Line Power Sequence

4.11.1 Power-Up Sequence

1. Hold RESET low until the power supplies are stable. Note: VA must be applied prior to VCP to

maintain the relationship specified in “Recommended Operating Conditions” on page 14. RESET

should be held low for a minimum of 1 ms after power supplies are stable.

2. Apply MCLK at the appropriate frequency, as discussed in Section 4.8. SCLK may be applied or set

to master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.

3. Bring RESET high.

LRCK

SCLK

MS B

LS B

MS B

LS B

AOUTA / AINxA

Left C ha nnel

Right C h an n el

SDIN

AOUTB / AINxB

MSB

Figure 32. I²S Format

LRCK

SCLK

MS B

LS B

MS B

LS B

L eft C han nel

Right C h an nel

SDIN

MSB

AOUTA / AINxA

AOUTB / AINxB

Figure 33. Left-Justified Format

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