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CS42L56 Datasheet(PDF) 22 Page - Cirrus Logic

Part # CS42L56
Description  Ultralow Power, Stereo Codec with Class H Headphone Amp
PDF  92 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42L56 Datasheet(HTML) 22 Page - Cirrus Logic

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22
DS851F2
CS42L56
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = GND = AGND, Logic 1 = VL, LRCK, SCLK, SDOUT CLOAD = 15 pF.
Notes:
20. After powering up the CS42L56, RESET should be held low after the power supplies and clocks are
settled. This specification is valid with the recommended capacitor on VDFILT.
21. When the RATIO[1:0] = ‘01’, the device will periodically extend the SCLK high time to compensate for
the resulting fractional MCLK/SCLK ratio.
Parameters
Symbol
Min
Max
Units
RESET pin Low Pulse Width
(Note 20)
1-
ms
MCLK Frequency
(See “Serial Port Clocking”
on page 47)
MHz
MCLK Duty Cycle
45
55
%
Slave Mode (Figure 8)
Input Sample Rate (LRCK)
Fs
(See “Serial Port Clocking”
on page 47)
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/tPs
-68•Fs
Hz
SCLK Duty Cycle
45
55
%
LRCK Setup Time Before SCLK Rising Edge
tss(LK-SK)
40
-
ns
SDOUT Setup Time Before SCLK Rising Edge
tss(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
ths(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
tss(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
ths
20
-
ns
Master Mode (Figure 9)
Output Sample Rate (LRCK)
Fs
(See “Serial Port Clocking”
on page 47)
Hz
LRCK Duty Cycle
45
55
%
SCLK Frequency
SCLK = MCLK mode
1/tPm
-
12.0000
MHz
All Other Modes
1/tPm
-68•Fs
Hz
SCLK Duty Cycle
RATIO[4:0] = ‘xxx00’ or ‘xxx11’
45
55
%
RATIO[4:0] = ‘xxx01’ (Note 21)
33
66
%
LRCK Time Before SCLK Falling Edge
tsm(LK-SK)
-±2
ns
SDOUT Setup Time Before SCLK Rising Edge
tsm(SDO-SK)
20
-
ns
SDOUT Hold Time After SCLK Rising Edge
thm(SK-SDO)
30
-
ns
SDIN Setup Time Before SCLK Rising Edge
tsm(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
thm
20
-
ns
Figure 8. Serial Port Timing (Slave Mode)
Figure 9. Serial Port Timing (Master Mode)
ths(SK-SDO)
//
//
//
//
//
//
//
//
tss(SD-SK)
MSB
MSB
LRCK
SCLK
SDOUT
SDIN
tss(LK-SK)
tP
ths
tss(SDO-SK)
//
//
//
//
thm(SK-SDO)
//
//
//
//
//
//
//
//
tsm(SD-SK)
MSB
MSB
LRCK
SCLK
SDOUT
SDIN
tPm
thm
tsm(SDO-SK)
//
//
//
//
//
//
tsm(LK-SK)



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