CS47L85 datasheet(93/370 Pages) CIRRUS

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CS47L85

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3723

(0E8Bh)

DRC2_ctrl4

10:5

DRC2_KNEE_IP

[5:0]

000000

DRC2 Input signal level at the

Compressor ‘Knee’.

000000 = 0dB

000001 = -0.75dB

000010 = -1.5dB

… (-0.75dB steps)

111100 = -45dB

111101 = Reserved

11111X = Reserved

4:0

DRC2_KNEE_O

P [4:0]

00000

DRC2 Output signal at the

Compressor ‘Knee’.

00000 = 0dB

00001 = -0.75dB

00010 = -1.5dB

… (-0.75dB steps)

11110 = -22.5dB

11111 = Reserved

R3724

(0E8Ch)

DRC2_ctrl5

9:5

DRC2_KNEE2_I

P [4:0]

00000

DRC2 Input signal level at the Noise

Gate threshold ‘Knee2’.

00000 = -36dB

00001 = -37.5dB

00010 = -39dB

… (-1.5dB steps)

11110 = -81dB

11111 = -82.5dB

Only applicable when

DRC2_NG_ENA = 1.

4:0

DRC2_KNEE2_

OP [4:0]

00000

DRC2 Output signal at the Noise

Gate threshold ‘Knee2’.

00000 = -30dB

00001 = -31.5dB

00010 = -33dB

… (-1.5dB steps)

11110 = -75dB

11111 = -76.5dB

Only applicable when

DRC2_KNEE2_OP_ENA = 1.

Table 15 DRC2 Control Registers

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded

DRC and digital mixing functions. If an attempt is made to enable a DRC signal path, and there are insufficient SYSCLK

cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be

affected under these circumstances.)

The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked

Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully

enabled.

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

CS47L85 Datasheet(PDF) 93 Page - Cirrus Logic

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