CS47L85 datasheet(96/370 Pages) CIRRUS

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CS47L85

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3789

(0ECDh)

HPLPF4_

15:0

LHPF4_COEFF

[15:0]

0000h

Low/High Pass Filter 4 Frequency

Coefficient

Refer to WISCE evaluation board control

software for the derivation of this field

value.

Table 16 Low Pass Filter / High Pass Filter Control

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the commanded

LHPF and digital mixing functions. If an attempt is made to enable an LHPF signal path, and there are insufficient SYSCLK

cycles to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be

affected under these circumstances.)

The FX_STS field in Register R3585 indicates the status of each of the EQ, DRC and LHPF signal paths. If an Underclocked

Error condition occurs, then this register provides readback of which EQ, DRC or LHPF signal path(s) have been successfully

enabled.

The status bits in Registers R1600 to R3192 indicate the status of each of the digital mixers. If an Underclocked Error

condition occurs, then these bits provide readback of which mixer(s) have been successfully enabled.

DIGITAL CORE DSP

The digital core provides seven programmable DSP processing blocks as illustrated in Figure 31. Each block supports 8

inputs (Left, Right, Aux1, Aux2, … Aux6). A 4-input mixer is associated with the Left and Right inputs, providing further

expansion of the number of input paths. Each of the input sources is selectable, and independent volume control is provided

for Left and Right input mixer channels. Each DSP block supports 6 outputs.

The functionality of the DSP processing blocks is not fixed, and a wide range of audio enhancements algorithms may be

performed. The procedure for configuring the CS47L85

DSP functions is tailored to each customer’s application; please

contact your local Cirrus Logic representative for more details.

For details of the DSP

Firmware requirements relating to clocking, register access, and code execution, refer to the “DSP

Firmware Control

” section.

DSPnLMIX_VOL2

DSPnLMIX_VOL3

DSPnLMIX_VOL4

DSPnLMIX_VOL1

DSPnLMIX_SRC1

DSPnLMIX_SRC3

DSPnLMIX_SRC4

DSPnLMIX_SRC2

DSPnRMIX_VOL2

DSPnRMIX_VOL3

DSPnRMIX_VOL4

DSPnRMIX_VOL1

DSPnRMIX_SRC1

DSPnRMIX_SRC3

DSPnRMIX_SRC4

DSPnRMIX_SRC2

DSP

DSPn Channel 1

DSPn Channel 2

DSPn Channel 3

DSPn Channel 4

DSPn Channel 5

DSPn Channel 6

CS47L85 supports 7 DSP blocks, ie. n = 1, 2, 3, 4, 5, 6 or 7

DSP1 Outputs:

(68h, 69h, 6Ah,

6Bh, 6Ch, 6Dh)

DSP2 Outputs:

(70h, 71h, 72h,

73h, 74h, 75h)

DSP3 Outputs:

(78h, 79h, 7Ah,

7Bh, 7Ch, 7Dh)

DSP4 Outputs:

(80h, 81h, 82h,

83h, 84h, 85h)

DSP5 Outputs:

(88h, 89h, 8Ah,

8Bh, 8Ch, 8Dh)

DSP6 Outputs:

(C0h, C1h, C2h,

C3h, C4h, C5h)

DSP7 Output:

(C8h, C9h, CAh,

CBh, CCh, CDh)

Figure 31 Digital Core DSP Blocks

CS47L85 Datasheet(PDF) 96 Page - Cirrus Logic

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