CS47L85 datasheet(94/370 Pages) CIRRUS

94 / 370 page

CS47L85

Rev 4.3

LOW PASS / HIGH PASS DIGITAL FILTER (LHPF)

The digital core provides four Low Pass Filter (LPF) / High Pass Filter (HPF) processing blocks as illustrated in Figure 30.

A 4-input mixer is associated with each filter. The 4 input sources are selectable in each case, and independent volume

control is provided for each path. Each Low/High Pass Filter (LHPF) block supports 1 output.

The Low Pass Filter / High Pass Filter can be used to remove unwanted ‘out of band’ noise from a signal path. Each filter

can be configured either as a Low Pass filter or High Pass filter.

CS47L85 supports 4 LHPF blocks, ie. n = 1, 2, 3 or 4

LHPFnMIX_VOL2

LHPFnMIX_VOL3

LHPFnMIX_VOL4

LHPFnMIX_VOL1

LHPFnMIX_SRC1

LHPFnMIX_SRC3

LHPFnMIX_SRC4

LHPFnMIX_SRC2

LHPF1 (60h)

LHPF2 (61h)

LHPF3 (62h)

LHPF4 (63h)

LHPF

Low-Pass filter (LPF) /

High-Pass filter (HPF)

Figure 30 Digital Core LPF/HPF Blocks

The LHPF1, LHPF2, LHPF3 and LHPF4 mixer control registers (see Figure 30) are located at register addresses R2304

(900h) through to R2335 (91Fh).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective LHPF processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the LHPF to which they are connected. Sample rate conversion

functions are available to support flexible interconnectivity -

see “Asynchronous Sample Rate Converter (ASRC)” and

“Isochronous Sample Rate Converter (ISRC)”.

The bracketed numbers in Figure 30,

e.g.,”(60h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The LHPF blocks should be kept disabled (LHPFn_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all digital

core functions should be held at 00h if SYSCLK is not enabled. SYSCLK must be present and enabled before selecting

other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The sample rate for the LHPF function is configured using the FX_RATE register - see Table 22. Note that the EQ, DRC

and LHPF functions must all be configured for the same sample rate. Sample rate conversion is required when routing the

LHPF signal paths to any signal chain that is asynchronous and/or configured for a different sample rate.

The FX_RATE register should not be changed if any of the associated *_SRCn registers is non-zero. The associated

*_SRCn registers should be cleared to 00h before writing a new value to FX_RATE. A minimum delay of 125us should be

allowed between clearing the *_SRCn registers and writing to the FX_RATE register. See Table 22 for further details.

The control registers associated with the LHPF functions are described in Table 16.

The cut-off frequencies for the LHPF blocks are set using the coefficients held in registers R3777, R3781, R3785 and R3789

for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus Logic

’s

WISCE evaluation board control software; please contact your local Cirrus Logic representative for more details.

CS47L85 Datasheet(PDF) 94 Page - Cirrus Logic

CS47L85 Datasheet(HTML) 94 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL