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CS47L85 Datasheet(PDF) 38 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 38 Page - Cirrus Logic

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CS47L85
38
Rev 4.3
DIGITAL AUDIO INTERFACE - TDM MODE
When TDM operation is used on the AIFnTXDAT pins, it is important that two devices do not attempt to drive the AIFnTXDAT
pin simultaneously. To support this requirement, the AIFnTXDAT pins can be configured to be tri-stated when not outputting
data.
The timing of the AIFnTXDAT tri-stating at the start and end of the data transmission is described in Figure 7 below.
BCLK
TXDAT
AIFnTXDAT enable time
AIFnTXDAT disable time
AIFnTXDAT undriven (tri-state)
AIFnTXDAT valid (CODEC output)
AIFnTXDAT valid
AIFnTXDAT undriven (tri-state)
Figure 7 Audio Interface Timing - TDM Mode
Test Conditions
The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNIT
TDM Timing - Master Mode
CLOAD (AIFnTXDAT) = 15pF to 25pF. BCLK slew (10% to 90%) = 3.7ns to 5.6ns.
AIFnTXDAT enable time from BCLK falling edge
0
ns
AIFnTXDAT disable time from BCLK falling edge
6
ns
TDM Timing - Slave Mode
CLOAD (AIFnTXDAT) = 15pF). BCLK slew (10% to 90%) = 3ns.
AIFnTXDAT enable time from BCLK falling edge
2
ns
AIFnTXDAT disable time from BCLK falling edge
12.2
ns
TDM Timing - Slave Mode
CLOAD (AIFnTXDAT) = 25pF). BCLK slew (10% to 90%) = 6ns
AIFnTXDAT enable time from BCLK falling edge
2
ns
AIFnTXDAT disable time from BCLK falling edge
14.2
ns



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