LTC9101-3/LTC9103

6

Rev. 0

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SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I2C Timing (Figure 4, Note 7 and 9)

fSCLK

Clock Frequency

l

1

MHz

t1

Bus Free Time

l

480

ns

t2

Start Hold Time

l

240

ns

t3

SCL Low Time

l

480

ns

t4

SCL High Time

l

240

ns

t5

SDAIN Data Hold Time

l

60

ns

Data Clock to SDAOUT Valid

l

250

ns

t6

Data Set-Up Time

l

80

ns

t7

Start Set-Up Time

l

240

ns

t8

Stop Set-Up Time

l

240

ns

tr

SCL, SDAIN Rise Time

l

120

ns

tf

SCL, SDAIN Fall Time

l

60

ns

SCL Fall to ACK Low

l

250

ns

ELECTRICAL CHARACTERISTICS The

l

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.

(Notes 3 and 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: This chipset includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative.

Note 4: The LTC9103 operates with a negative supply voltage (with

respect to AGND). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

Note 5: tDIS is the same as tMPDO defined by IEEE 802.3.

Note 6: The LTC9101-3 digital interface operates with respect to DGND. All

logic levels are measured with respect to DGND.

Note 7: Guaranteed by design, not subject to test.

Note 8: The IEEE 802.3 defines MPS as the set of minimum PSE and PD

input current requirements to maintain power. An LTC9101-3/LTC9103

port resets its MPS timer when VSENSEn – VSSKn ≥ VHOLD for tMPS and

removes port power when VSENSEn – VSSKn ≥ VHOLD for a period longer

than tDIS. See Disconnect section.

Note 9: Values Measured at VIHD.

Note 10: Load characteristics of the LTC9103 during Mark: 7V < (AGND –

VOUTn) < 10V.

Note 11: The I2C device address is fixed in software with a factory-default

value of 0x20 (7-bit address b0100000). The state of the AD[3:0] bits may

be reconfigured through a user-defined Configuration package. See Bus

Addressing.

Note 12: Do not source or sink current from CAP1, CAP2, CAP3 and CAP4.

Note 13: Port current and port power measurements depend on sense

resistor value (0.1Ω typical). See External Component Selection for details.

Note 14: See Inrush Control for details on inrush threshold selection.