LTC4271 datasheet(22/30 Pages) AD

22 / 30 page

LTC9101-3/LTC9103

Rev. 0

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APPLICATIONS INFORMATION

Table 7. Port LEDs and Corresponding LED Data Variables for an

8-Port System

PORT

PORT LED

SERIAL DATA

Status

Fault

Status

Fault

Status

Fault

Status

Fault

Status

Fault

Status

A10

Fault

A11

Status

A12

Fault

A13

Status

A14

Fault

A15

Note: This sequence is continued for a 16-port application.

In addition, the LTC9101-3 also provides a Supply

Overload LED bit through the OVR pin, which gives

indication that the LTC9101-3/LTC9103 PSE application

has either denied power, revoked power, or is near the

power limit. The Supply Overload LED fault conditions are

detailed in the Power Management and System Telemetry

sections.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network

segments (including PoE circuitry) be electrically isolated

from the chassis ground of each network interface device.

However, network segments are not required to be iso-

lated from each other, provided that the segments are

connected to devices residing within a single building on

a single power distribution system.

If the PSE is part of a larger system, contains additional

external non-Ethernet ports, or must be referenced to pro-

tective ground for some other reason, the PoE subsystem

must be electrically isolated from the rest of the system.

The LTC9101-3/LTC9103 chipset simplifies PSE isolation

by allowing the LTC9101-3 chip to reside on the non-iso-

lated side. There it can receive power from the main logic

supply. Isolation between the LTC9101-3 and LTC9103 is

implemented using a proprietary transformer-based com-

munication protocol. Additional details are provided in

the High-Speed Data Interface section of this data sheet.

For autonomously managed PoE switches, the isolation

requirement can be met by using an isolated main power

supply for the entire device. This strategy can be used

if the device has no electrically conducting ports other

than twisted-pair Ethernet. The LTC9101-3 may directly

connect to the LTC9103s in the above circumstances, or

if the system already provides isolation.

EXTERNAL COMPONENT SELECTION

Power Supplies

The LTC9101-3/LTC9103 requires two supply voltages to

operate. VDD requires 3.3V (nominally) relative to DGND.

VEE requires a negative voltage of between –51V to –57V.

Digital Power Supply

VDD provides digital power for the LTC9101-3 proces-

sor. A ceramic decoupling cap of at least 0.1µF should

be placed from each VDD to DGND, as close as practical

to each LTC9101-3. In addition, each LTC9101-3 must

include a bulk cap of 10µF for robust surge immunity.

A 1.2V core voltage supply is generated internally and

requires a 1µF ceramic decoupling cap between the CAP1

pin and DGND and between CAP2 and DGND.

In systems using ADI’s proprietary isolation, VDD should

be delivered by the system's non-isolated 3.3V supply.

To maintain required isolation, LTC9103 AGND and

LTC9101-3 DGND must not be connected. If using the

direct connection scheme, the LTC9101-3 DGND must

be connected to LTC9103 VEE.

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