LTC4271 datasheet(11/30 Pages) AD

11 / 30 page

LTC9101-3/LTC9103

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

LTC9101-3

CFG[2:0] (Pins 3, 2, 1 Respectively): Device

Configuration Inputs. Tie the configuration pins to set the

number of ports and connected LTC9103s. See DEVICE

CONFIGURATION for details.

LEGACY (Pin 5): Legacy Mode Input. Tie the LEGACY

pin to DGND for Legacy Mode Operation. Leave floating

for IEEE 802.3at compliant Operation. Legacy Mode is

continuously and globally updated based on pin state.

PC (Pin 6): LED Shift Register Parallel Capture Output.

This pin provides the parallel capture strobe for external

shift registers. PC must be followed locally by a Schmitt

trigger to drive the downstream shift registers.

CAP[2:1] (Pins 7, 23 Respectively): Core Power Supply

Bypass Capacitors. Connect each pin to a 1µF capacitance

to DGND for the internal 1.2V regulator bypass. Do not

use other capacitor values. Do not source or sink current

from this pin.

CPD (Pin 8): Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data transformer.

CND (Pin 9): Clock Transceiver Negative Input Output

(Digital). Connect to CNA through a data transformer.

DPD (Pin 10): Data Transceiver Positive Input Output

(Digital). Connect to DPA through a data transformer.

DND (Pin 11): Data Transceiver Negative Input Output

(Digital). Connect to DNA through a data transformer.

VDD (Pins 12, 19, 24): VDD IO Power Supply. Connect

to a 3.3V power supply relative to DGND. Each VDD pin

must be locally bypassed with at least a 0.1µF capacitor.

A 10µF bulk capacitor must be connected across VDD for

increased surge immunity.

SD (Pin 13): LED Shift Register Data Output. This pin

provides the data for external shift registers. SD must be

followed locally by a Schmitt trigger to drive the down-

stream shift registers.

RESET (Pin 14): Reset Input, Active Low. When RESET

is low, the LTC9101-3/LTC9103 is held inactive with all

ports off and all internal registers reset. When RESET is

pulled high, the LTC9101-3/LTC9103 begins normal oper-

ation. RESET can be connected to an external capacitor

or RC network to provide a power turn-on delay. Internal

filtering of RESET prevents glitches less than 1µs wide

from resetting the LTC9101-3/LTC9103. Internally pulled

up to VDD.

OVR (Pin 15): Supply Overload Indicator Output, Active

Low. The OVR pin may be used to drive an LED through

a current limiting resistor.

SDAOUT (Pin 16): Serial Data Output, Open Drain Data

Output for the I2C Serial Interface Bus. The LTC9101-3

uses two pins to implement the bidirectional SDA func-

tion to simplify opto isolation of the I2C bus. To imple-

ment a standard bidirectional SDA pin, tie SDAOUT and

SDAIN together. See Applications Information for more

information.

SDAIN (Pin 17): Serial Data Input. High impedance data

input for the I2C serial interface bus. The LTC9101-3

uses two pins to implement the bidirectional SDA func-

tion to simplify opto isolation of the I2C bus. To imple-

ment a standard bidirectional SDA pin, tie SDAOUT and

SDAIN together. See Applications Information for more

information.

SCL (Pin 18): Serial Clock Input. High impedance clock

input for the I2C serial interface bus. The SCL pin should

be connected directly to the I2C SCL bus line. SCL must

be tied high if the I2C serial interface bus is not used.

SC (Pin 20): LED Shift Register Clock Output. This pin

provides the clock signal for external shift registers. SC

must be followed locally by a Schmitt trigger to drive the

downstream shift registers.

DGND (Pins 22, 25): Digital Ground. DGND must be con-

nected to the return from the VDD supply.

LTC4271 Datasheet(PDF) 11 Page - Analog Devices

LTC4271 Datasheet(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL