LTC4271 datasheet(10/30 Pages) AD

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LTC9101-3/LTC9103

Rev. 0

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PIN FUNCTIONS

LTC9103

CAP3 (Pin 1): Analog Internal 3.3V Power Supply Bypass

Capacitor. Connect a 1µF ceramic cap to VEE. A 3.3V power

supply may be connected to this pin to improve power

supply efficiency. The EXT3 pin must be pulled to CAP3

to shut off the internal 3.3V regulator if power is supplied

externally. Do not source or sink current from this pin.

EXT3 (Pin 2): External 3.3V Enable. Connect the EXT3

pin to CAP3 to shut off the internal 3.3V regulator when

power is supplied externally. Float or connect to VEE for

internal regulator operation.

VSSK[8:1] (Pins 47, 46, 39, 38, 15, 14, 7, 6

Respectively): Kelvin Sense to VEE. Connect VSSKn to

VEE side of sense resistor for port n through a 0.1Ω resis-

tor. Do not connect directly to VEE plane. See Kelvin Sense

Layout Requirements.

SENSE[8:1] (Pins 48, 45, 40, 37, 16, 13, 8, 5

Respectively): Current Sense Input, Port n. SENSEn mon-

itors the external MOSFET current via a 0.1Ω sense resis-

tor between SENSEn and VSSKn. If the voltage across the

sense resistor reaches the current limit threshold ILIM, the

GATEn pin voltage is lowered to maintain constant current

in the external MOSFET. See Applications Information for

further details. If the port is unused, tie SENSEn to VEE.

OUT[8:1] (Pins 49, 44, 41, 36, 17, 12, 9, 4 Respectively):

Output Voltage Monitor, Port n. Connect OUTn to the

output port. A current limit fold-back circuit limits the

power dissipation in the external MOSFET by reducing the

current limit threshold when the drain-to-source voltage

exceeds 10V. A 500k resistor is connected internally from

OUTn to AGND when the port is idle. If the port is unused,

the OUTn pin must float.

GATE[8:1] (Pins 50, 43, 42, 35, 18, 11, 10, 3

Respectively): Gate Drive, Port n. Connect GATEn to the

gate of the external MOSFET for port n. When the MOSFET

is turned on, the gate voltage is driven to 12V (typ) above

VEE. During a current limit condition, the voltage at GATEn

will be reduced to maintain constant current through the

external MOSFET. If the fault timer expires, GATEn is

pulled down, turning the MOSFET off and raising a port

fault event. If the port is unused, the GATEn pin must float.

ID[1:0] (Pin 52, 51 respectively): Transceiver ID. Sets

the address of the LTC9103 on the multidrop high-speed

data interface. ID numbering must start at 00b. Tie high

by connecting to CAP3. Tie low by connecting to VEE. The

first LTC9103 must have address 00b and, if present, the

second must have address 01b.

PWRIN (Pin 55): Startup Regulator Bypass and External

Low Voltage Supply Input. Power for the internal 4.3V

and 3.3V internal supplies. An internal regulator maintains

the voltage of this pin above 6V. An external resistor or

supply may be connected to this node to improve the

power efficiency of the LTC9103. Connect a 1µF capacitor

between this pin and VEE.

AGND (Pin 56): Analog Ground.

PWRMD[1:0] (Pin 57, 58 Respectively): Maximum

Power Mode Input. These pins must be left unconnected

for all LTC9101-3/LTC9103 applications.

CAP4 (Pin 59): Analog Internal 4.3V Power Supply

Bypass Capacitor. Connect a 1µF ceramic cap to VEE. Do

not source or sink current from this pin.

VEE (Pins 60, 65): Main PoE Supply Input. Connect to a

–51V to –57V supply, relative to AGND.

DNA (Pin 61): Data Transceiver Negative Input Output

(Analog). Connect to DND through a data transformer.

DPA (Pin 62): Data Transceiver Positive Input Output

(Analog). Connect to DPD through a data transformer.

CNA (Pin 63): Clock Transceiver Negative Input Output

(Analog). Connect to CND through a data transformer.

CPA (Pin 64): Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a data transformer.

Common Pins

NC, DNC (LTC9101-3 Pin 4, 21; LTC9103 Pins 19-34,

53, 54: All pins identified with “NC” or “DNC” must be

left unconnected.

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