LTC4271 datasheet(23/30 Pages) AD

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LTC9101-3/LTC9103

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Main PoE Power Supply

VEE is the main isolated PoE supply that provides power

to the PDs. Because it supplies a relatively large amount

of power and is subject to significant current transients,

it requires more design care than a simple logic supply.

For minimum IR loss and best system efficiency, set VEE

near maximum amplitude (57V), leaving enough margin

to account for transient over or undershoot, temperature

drift, and the line regulation specifications of the particular

power supply used.

A bypass capacitor and a transient voltage suppressor

(TVS) between each LTC9103 AGND and VEE are very

important for reliable operation. If a short circuit occurs

at one of the output ports it can take as long as 1µs for

the LTC9103 to begin regulating the current. During this

time the current is limited only by the small impedances in

the circuit; a high current spike typically occurs, causing a

voltage transient on the VEE supply and possibly causing

the LTC9101-3/LTC9103 to reset due to a UVLO fault.

A 1µF, 100V X7R capacitor and an SMAJ58A near each

LTC9103 are recommended to minimize spurious resets.

An electrolytic bulk capacitor of at least 47µF, 100V and a

bulk TVS are also recommended per system.

LTC9103 Low Voltage Power Supplies

The LTC9103 includes internal voltage regulators that

generate low voltage supplies directly from the main PoE

power supply. At startup, an internal regulator generates

6V at PWRIN, drawing power from AGND. Internal 4.3V

and 3.3V rails are sub-regulated from PWRIN. The PWRIN

pin requires a local 1µF, 100V bypass capacitor.

Pull-up resistors can be connected from PWRIN to

AGND to dissipate heat outside the LTC9103 package.

Optionally, an external power supply can be connected

to PWRIN to override the startup regulator and reduce

power dissipation.

Figure 15 shows a pull-up resistor configuration with the

internal 3.3V regulator. Bypass resistors R1, R2, R3, and

R4 draw heat away from the LTC9103s. Note that the

voltage of the PWRIN pin changes based on the LTC9103

operating mode and its corresponding current consump-

tion. If more current is consumed than the bypass resis-

tors provide, the startup regulator maintains the voltage at

6V typical. The LTC9103 can operate without the pull-up

resistors in space-constrained applications.

In applications with an external PWRIN supply, a 6.5V

regulator provides an optimum voltage to override the

internal 6V start-up regulator, while minimizing the

LTC9103 device heating. The external supply may be

shared across both LTC9103s.

A 3.3V power supply can be connected directly to the

CAP3 pin, as shown in Figure 16. This provides the most

power efficient sleep mode. When supplying external 3.3V

power, tie the EXT3 pin to CAP3. This will disable the

internal 3.3V regulator and prevent power back-feed. The

3.3V regulator must power up within tCAP3EXT specified in

the Electrical Characteristics table.

If using the direct connection scheme, the 3.3V reg-

ulator that supplies the LTC9101-3 can also supply

the LTC9103s. This is the preferred option when the

LTC9101-3 and LTC9103 are on the same side of the

system isolation barrier.

91013 F15

1µF

100V

1µF

100V

1µF

100V

1µF

10k

1/2W

10k

1/2W

1µF

47µF

100V

10k

1/2W

10k

1/2W

1µF

VEE

AGND

CAP3

EXT3

LTC9103

VEE

AGND

CAP3

EXT3

CAP4

PWRIN

LTC9103

1µF

100V

1µF

CAP4

PWRIN

Figure 15. Power Supply Configuration with Internal 3.3V Supply

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