MPC8540 datasheet(1015/1302 Pages) FREESCALE

1015 / 1302 page

RapidIO Functionality

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-91

17.5.1.1 8/16 LP-LVDS Layer Functionality Lists

The physical layer 8/16 LP-LVDS (low-power, low-voltage differential signaling) layer

functionality is subdivided into individual lists.

Table 17-87 lists requirements for basic 8/16 LP-LVDS physical layer functionality for the device.

Note that for device ID-related functions, the device ID for the RapidIO controller is set by

power-on reset signals as described in Section 4.4.3.11, “RapidIO Device ID.”

Table 17-87. General Device 8/16 LP-LVDS Physical Layer Basic

Functionality List

Item No.

Item Functionality

Meets Reqs?

CLK signal(s) rising edge is on the 32-bit boundary

CLK signal(s) toggle every clock (true free running clock).

RIO_TFRAME/RIO_RFRAME signal only toggles on the 32-bit boundary

RIO_TFRAME/RIO_RFRAME signal only toggles to mark the first byte of a control symbol or the

first byte of a new packet

RIO_RFRAME/RIO_TFRAME signal is associated with RIO_RCLK/RIO_TCLK

Device meets target AC specifications

Device follows the link initialization and training procedure

7A ACTION: Device responds to link-request/send-training control symbol with 256 training patterns

followed by at least one idle control symbol

7B DETAIL: Device port is enabled to transmit or receive packets only after device is both sending

and receiving idle control symbols

7C DETAIL: Training pattern is not embedded in a packet or used to terminate a packet

Training symbol is correct for port width

16-bit ports can function as 8-bit ports

Control symbols are 16 bits followed by an inverted 16-bit copy.

Undefined control symbols are treated as idle control symbols.

Device responds to a throttle control symbol with a pacing idle control symbol within the specified

60 data ticks time

Device follows native RapidIO ordering rules at flow level 1

13A. DETAIL: Read packets are transmitted at priority level 1.

13B. DETAIL: Write packets are transmitted at priority level 1.

13C. DETAIL: Response packets are transmitted at priority level 1, 2, or 3.

13D. DETAIL: Packets of the same priority level cannot pass each other.

13E. DETAIL: Packets of higher priority may pass packets of a lower priority level.

MPC8540 Datasheet(PDF) 1015 Page - Freescale Semiconductor, Inc