MPC8540 datasheet(1023/1302 Pages) FREESCALE

1023 / 1302 page

RapidIO Functionality

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

17-99

Table 17-94 lists the functionality for this controller in transmitting a packet (a slave device is

required to generate response packets).

Table 17-95 lists the functionality for this controller in receiving a packet.

Logical layer errors are generally not recoverable in hardware. They may be recoverable in

software. The device is always the target of a packet for error detection. Table 17-96 lists

detectable errors.

Table 17-93. General Device Common Transport Layer Basic Functionality List

Item No.

Item Functionality

Meets Reqs?

All necessary CSRs (command and status registers) exist and can be read.

1A. DETAIL: Base device ID CSR; reset value is application and implementation dependent

(end point devices only)

1B. DETAIL: Host base device ID lock CSR; Host_base_deviceID field reset value is 0xFFFF

1C. DETAIL: Component tag CSR; reset value is 0x0000_0000

Writable CSR fields can be written

Table 17-94. General Device Common Transport Layer Packet Transmission List

Item No.

Item Functionality

Meets Reqs?

TT field is always logic 0s (small device ID fields)

End point-free switch responds to maintenance requests with the c_count = 0 when

received, otherwise decrement hop_count and route to proper output port

Maintenance response packets are issued with the hop_count field set to 0xFF

Table 17-95. General Device Common Transport Layer Packet Reception List

Item No.

Item Functionality

Meets Reqs?

Response packets are sent with the target and destination fields reversed from the

corresponding request packet

Table 17-96. General Device Common Transport Layer Detectable Errors List

Item No.

Item Functionality

Meets Reqs?

Received reserved TT field encoding

MPC8540 Datasheet(PDF) 1023 Page - Freescale Semiconductor, Inc