MPC8540 datasheet(1024/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-100

Freescale Semiconductor

RapidIO Interface

17.5.3 Logical Layer Functionality Lists

The logical layer functionality is subdivided into individual lists.

Table 17-97 lists the requirements for basic device functionality and the compliance of this

controller. A class 1 device is always the target of a request transaction.

Table 17-97. General Device Logical Layer Basic Functionality List

Item No.

Item Functionality

Meets Reqs?

The address field of a packet is a double-word (8 byte) aligned address.

Multiple double-word data payloads are linear starting at the specified address.

Multiple double-word data payloads are aligned to a double-word boundary.

Multiple double-word data payloads are not required to be aligned to the transfer size boundary.

Sub-double-word data payloads have a defined data payload, properly aligned and padded to a

double-word boundary.

Response packets have the transaction ID of the associated request packet.

Responses that are not expected to have a data payload must not have a data payload.

Responses may not contain a data payload if the response status is ERROR.

All necessary CARs (capabilities registers) exist and can be read.

9A. DETAIL: Device identity CAR; value is vendor- and implementation-dependent.

9B. DETAIL: Device information CAR; value is vendor- and implementation-dependent

9C. DETAIL: Assembly identity CAR; value is vendor- and implementation-dependent

9D. DETAIL: Assembly information CAR; value is vendor- and implementation-dependent

9E. DETAIL: Processing element features CAR; value is implementation-dependent; must indicate

support for 34-bit address format packets

9F. DETAIL: Switch port information CAR; value is implementation-dependent (switch devices only)

9G. DETAIL: Source operations CAR; value is implementation-dependent (end point devices only)

9H. DETAIL: Destination operations CAR; value is implementation-dependent (end point devices

only).

All necessary CSRs (command and status registers) exist and can be read.

10A. DETAIL: Processing element logical layer control CSR: reset value of the extended addressing

control field is 0b001 (end point devices only)

Writable CSR fields can be written.

All registers in the extended features data structure are double-word (8 byte) aligned (the three lsbs

of the extended features pointers must be logic zeros).

All extended features blocks lie within the extended features space in the register address map.

Extended features list is terminated with an extended features pointer value of logic zeros

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