MPC8540 datasheet(1026/1302 Pages) FREESCALE

1026 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

17-102

Freescale Semiconductor

RapidIO Interface

17.6 RapidIO Errors

RapidIO errors are classified under three categories:

•

Recoverable errors—The RapidIO controller supports hardware error detection and

recovery mechanism as specified in the Parallel RapidIO Interconnect Specification. The

RapidIO controller detects and attempts to recover from corrupt packet and control symbol

errors and general protocol errors. In these cases, the appropriate bit is set in the RapidIO

recoverable error detect register. Logging of information in capture registers may or may

not take place. See Table 17-100 for specifics regarding the RapidIO controller.

•

Notification errors—The RapidIO controller detects many hardware nonrecoverable errors

that are non-fatal such as exceeded threshold counts (as defined in PERTR and PRTR).

Upon detection of a notification error the appropriate bit is set in the port notification/fatal

error detect register (PNFEDR) and an interrupt is generated if enabled in the port

notification/fatal error interrupt enable register (PNFEIER). Hardware continues to operate

after notification errors.

•

Fatal errors—The RapidIO controller also detects a number of fatal errors that are hardware

nonrecoverable, such as time-outs. Upon detection of a fatal error, relevant information

may be logged (PECSR[V] indicates successful capture) in the error packet capture

registers (EPCRn) if the appropriate error detect is enabled (PNFEDiR). An interrupt is

generated if the appropriate fatal error interrupt is enabled in the port notification/fatal error

interrupt enable register (PNFEIER). The RapidIO hardware either goes into training

mode, or remains in the OK state based on the error type.

If the valid bit of the port error capture status register (PECSR[V]) is set, the information in error

packet capture registers EPCR0–EPCR3 is valid:

Fatal errors caused by a bad link invoke training in an attempt to recover the link. If

communication is not re-established, a RESET is required to reconcile RapidIO’s internal queues

to resume normal operation. Table 17-100 lists the recoverable errors detected by the RapidIO

implementation and the resulting actions taken.

Table 17-100. Recoverable Errors Detected by RapidIO Controller

Error

Description

Action

Capture Registers

Inbound corrupt control

symbol

Received a control symbol in which

true does not match complement

counterpart

Sends “PACKET_NOT_

ACCEPTED” ack with “Error

on control symbol” cause

No information logged in

capture register(s)

Inbound packet/control

symbol with S-bit parity error

Received a packet or a control

symbol with an S-bit parity error

Sends “PACKET_NOT_

ACCEPTED” ack with “S-bit

parity error” cause

No information logged in

capture register(s)

Inbound out-of-sequence ack

symbol

Received an ack control symbol with

an unexpected ackID

Starts link recovery process

No information logged in

capture register(s)

MPC8540 Datasheet(PDF) 1026 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1026 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL