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TLS2205 Datasheet(PDF) 11 Page - Texas Instruments |
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TLS2205 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 31 page ![]() SLFS040 – DECEMBER 1993 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 PRINCIPLES OF OPERATION VCM current-loop stability is accomplished using the filter at CMPI and CMPO. This filter has the following transfer function: (Rcmp (Ccmp2 + Cmp1) s + 1) Ccmp2 s (Rcmp Ccmp1 s + 1) where: s is a Laplace operator VCM retract The TLS2205 integrated retract circuit eliminates the need for external power supply isolation devices. The retract mode is triggered by the voltage monitor fault logic signal. The retract power path is coupled from the spindle-motor back-EMF to the RETOUT MOS high-side driver via CRET. After the retract control block has been triggered by a loss of power, the following events occur: 1. The system control logic is reset to the power-up state. All bias is disabled (including VDD); all power outputs are disabled. 2. The retract control circuit locks the VCMB low-side driver on and disables the VCMB high-side driver. 3. The retract control circuit disables the VCMA low- and high-side drivers. 4. RETOUT is enabled, and RETSET is used to control the voltage applied to RETOUT. The spindle back-EMF-mode voltage supplies the energy necessary to retract the VCM (see Figure 3). The energy stored in the capacitor (CVDD) connected to VDD is used to control the RETOUT and VCMB power devices. The value of this capacitor can be calculated based on ~ 2 A of retract-mode discharge current and the time to retract t the VCM. The RETOUT control equation is: VVCMA = Vbe [1 + (Rrset1/Rrset2)] CVDD = 2 A ( t) VVCMA where: Vbe is the base-to-emitter junction voltage 0.7 V. Example: Assume: Rrset1 = 62 k Rrset2 = 100 k t = 6 ms max Therefore: CVDD = 2 A (5 ms) 0.7 V (1 + 62 k /100 k ) = 0.009 F 0.01 F t = 0.01 F [0.7 V (1 + 62 k /100 k )] 2 A = 5.7 ms |
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