SLFS040

– DECEMBER 1993

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

24

PRINCIPLES OF OPERATION

Port-C system control bit definitions (continued)

SPNMODE

SPNMODE is used to determine whether the spindle charge pump or DAC is driving the spindle-control

amplifiers. When SPNMODE is asserted, the spindle current is controlled by the DAC.

COMM

The COMM bit is used to commutate the spindle driver in the start mode. For every low-to-high state change,

the spindle inverter advances one step.

UPOLAR

UPOLAR controls the spindle-motor drive mode. When this bit is low, the TLS2205 drives the motor in a standard

bipolar mode. When this bit is high, CTDRV is switched low and the internal high-side drivers are disabled. An

external pnp transistor can be switched on using CTDRV, and the device operates in the unipolar mode.

NHALLS

The NHALLS bit controls which commutation mode is used by the spindle-control logic. When this bit is 0, the

TLS2205 uses the Hall sense inputs (HU, HV, HW) to directly commutate the spindle motor. When this bit is 1,

the TLS2205 switches into the back-EMF commutation mode. The Hall inputs have no meaning in the back-EMF

commutation mode. However, the Hall logic inputs determine the motor inverter power-up initial state. The Hall

inputs are internally tied low.

START

This bit controls the spindle-motor driver logic inputs and auxiliary I/O signals (see Table 7).

SPNENA

The SPNENA bit enables the spindle-motor drivers. The charge-pump control path (SPNCOMP) is not affected

by this bit. When this bit is 0, the spindle-motor power drivers are disabled (motor phases U, V, W are Hi-Z) but

not powered down. When this bit is 1, the spindle drivers are enabled.

AUXIN/AUXOUT functional description

Port-C controls (for spindle-motor operation in back-EMF mode)

The spindle-motor operation modes are shown in the description section of Table 7. To fully understand this

figure, the functional block diagram must be used in conjunction with port C.

As an example:

1.

To start the drive (START MODE), START (bit 1) = 0, AUX1 (bit 10) = 1, and AUX0 (bit 9) = 1. As a result,

Phase is the signal seen on the internal PCLK line, SCK is the signal seen on the internal PADV line, and

NHphase is the signal seen at AUXOUT.

2.

Once the spindle is spinning at approximately 20% of rated speed, the drive is switched into RUN

MODE 0 (START = 0, AUX1 = 0, and AUX0 = 0). As a result, phase is the signal seen on the internal

PCLK line and NHphase is the signal seen on the internal PADV line and at AUXOUT.

3.

After the spindle reaches operational speed, the drive is switched into RUN MODE 3 (START = 0,

AUX1 = 1, AUX0 = 1). As a result, AUXIN is the signal seen on the internal PCLK line, NHphase is the

signal seen on the internal PADV line, and Fspn is the signal seen at AUXOUT.