SLFS040

– DECEMBER 1993

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

17

PRINCIPLES OF OPERATION

spindle-speed control

The TLS2205 provides a frequency-locked-loop speed-control system. Figure 7 is an illustration of the

spindle-speed control loop. This system operates by generating a once-around signal from either Hall or

back-EMF state changes. This signal is then divided by either 12 (for 8-pole motor) or 18 (for 12-pole motor)

(port B bit 11). This signal is called Fspn. Fspn is a once-around spindle-motor clock. Fspn is compared to a

signal that is generated from the MTRCLK (Fref). Fref is generated by dividing the MTRCLK by 16, then dividing

again by the value stored in the spindle-reference counter (port B bits 0

–10). The Fref and Fspn signals are

compared, and the time domain error is fed to the charge pump every other rotation. The charge-pump output

is a speed error signal that is filtered by a PI filter at SPNCOMP. The output of this filter commands the spindle

current. The spindle rotation TACH output (Fspn) or the back-EMF commutation clock (NHphase) can be directly

measured at AUXOUT. AUXIN can be used to provide an external index signal for motor commutation instead

of using the speed feedback circuit. See Table 7 for a description of the spindle-motor operating modes.

Spindle rotational speed is calculated from the equation below:

where:

R is the value stored in port B bits 0

–11 (0 < R < 2047)

Spindle-speed regulation

1 / [( 8

R) + 1] (%)