SLFS040

– DECEMBER 1993

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

19

PRINCIPLES OF OPERATION

serial-port timing

The TLS2205 is designed to receive data in four basic formats: TMS320C2x burst mode, TMS320C2x

continuous mode, 8-bit microprocessor format mode, and 16-bit microprocessor format mode.

The serial port uses three control lines: SCLK (serial-port clock), SDATA (serial-port data), and SPSZ (serial-port

select not). The SCLK line is a serial data clock with data rates up to 12 MHz; SCLK should have a 50% duty

cycle. The SDATA line is the actual serial data input and must be synchronous with the leading edge of SCLK.

SPSZ is the serial-port select input and is internally tied low to be synchronous with the leading edge of SCLK.

If the TMS320C2x DSP is used in burst or continuous modes, the following bits in the ST1 register should be

set (1) or reset (0) as indicated:

BIT NAME

BIT #

SET/RESET

RESULT

TXM (transmit mode)

2

1

FSX is configured as an output

FO (format)

3

0

16-bit mode selected

FSM (framing sync)

5

1

A framing sync is generated

Refer to the TMS320C2x User

’s Guide for further details.

burst mode

In the serial-port burst-mode operation, transfers are separated in time by periods of no serial-port activity (the

serial port does not operate continuously). For burst-mode operation, the SPSZ line must be low on the

negative-going edge of SCLK before data is read in; then 16 data bits can be read in. All continuing data bits

are ignored until the SPSZ line is toggled from low to high to low. Then data is valid on the first negative-going

clock. See Figure 8 for details.

SCLK

SPSZ

SDATA

Frame Sync

ID1

12 Data Bits

Device

Port

ID0 PT1 PT0 SR11 SR10

SR11

SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

ID1

ID0 PT1 PT0

NOTE: ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.

Figure 8. Serial-Port Burst-Mode Operation