NXP Semiconductors

SE050

Plug & Trust Secure Element

Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical

values are only referenced for information. They are subject to change without notice.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

[3]

[2]

0.25 x

tIOWx_min

μs

tfIO

I/O Input fall time

Input/reception mode

[1]

[2]

1

μs

[3]

[2]

0.25 x

tIOWx_min

μs

trOIO

I/O Output rise time

Output/transmission mode; CL

= 30 pF

[2]

0.1

μs

tfOIO

I/O Output fall time

Output/transmission mode; CL

= 30 pF

[2]

0.1

μs

Inputs: CLK and RST_N

fCLK

External clock frequency

in ISO/IEC 7816 UART

applications

tCLKW, tamb and VCC in their

specified limits

[4]

0.85

11.5

MHz

tCLKW

Clock pulse width i.r.t. clock

period (positive pulse duty

cycle of CLK)

40

60

%

trCLK

CLK input rise time

[5]

[6]

tfCLK

CLK input fall time

[2]

[6]

[6]

trRST

RST_N input rise time

[2]

400

μs

tfRST

RST_N input fall time

[2]

[7]

400

μs

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)...continued

[1]

At minimum IO1 input signal HIGH or LOW level voltage pulse width of 3.2 μs. This timing specification applies to ISO7816 configurations down to a

minimum etu duration of 16 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x96, (Fi/Di)=(512/32)), for example.

[2]

tr is defined as rise time between 10 % and 90 % of the signal amplitude.

[3]

At minimum IO1 input signal HIGH or LOW level voltage pulse width of less than 3.2 μs. This timing specification applies to ISO7816 configurations

beyond the conditions listed in note [2], down to a minimum etu duration of 8 CLK cycles at a maximum CLK frequency of 5 MHz (TA1=0x97, (Fi/

Di)=(512/64)), for example. An 8 CLKs/etu @ fclk = 5 MHz configuration results in tIOWx_min = 1.6 μs, and in a time of 400 ns for trIO_max and tfIO_

max, matching the (Fi/Di)=(512/64) speed enhancement requirements of ETSI TS 102 221.

[4]

ISO/IEC 7816 I/O applications have to supply a clock signal to input CLK in the frequency range of 1 MHz to 10 MHz nominal. A ± 15 % tolerance range

yields the allowed limits of 0.85 MHz and 11.5 MHz.

[5]

During AC testing the inputs CLK, RST_N, and IO1 are driven at 0 V to +0.3 V for a LOW input level and at VCC − 0.3 V to VCC for a HIGH input level.

Clock period and signal pulse (duty cycle) timing is measured at 50 % of VCC, see Figure 18.

[6]

The maximum CLK rise and fall time is 10 % of the CLK period 1/fCLK - with the following exception: In the CLK frequency range of 1 MHz to 5 MHz the

maximum allowed CLK rise and fall time is 50 ns, if 10 % of the CLK period is shorter than 50 ns.

[7]

The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.

Note: tf is defined as fall time between 90 % and 10 % of the signal amplitude.

Conditions: Tamb = -25 °C to +85 °C, unless otherwise specified.

Symbol Parameter

Conditions

Typ[1]

Max

Unit

Input/Output: LA, LB

Table 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise

specified

SE050

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Product data sheet

Rev. 3.5 — 22 August 2022

504935

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