LTC4253IGN datasheet(11/32 Pages) LINER

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LTC4253

4253f

the fault current as measured at SENSE. Compensation

capacitor, CC, at GATE stabilizes this loop. A comparator

monitors GATE to ensure that it is low before allowing an

initial timing cycle, GATE ramp up after an overvoltage

event or restart after a current limit fault. During GATE

start-up, a second comparator detects GATE within 2.8V

of VIN before PWRGD1 can be set and power good

sequencing starts.

DRAIN (Pin 10): Drain Sense Input. Connecting an exter-

nal resistor, RD between this pin and the MOSFET's drain

(VOUT) allows voltage sensing below 6.15V and current

feedback to TIMER. A comparator detects if DRAIN is

below 2.385V and together with the GATE high compara-

tor, sets the PWRGD1 flag. If VOUT is above VDRNCL, the

DRAIN pin is clamped at approximately VDRNCL. RD cur-

rent is internally multiplied by 8 and added to TIMER's

200

µAduringacircuitbreakerfaultcycle.Thisreducesthe

fault time and MOSFET heating.

OV (Pin 11): Over-Voltage Input. The active high threshold

at the OV pin is set at 6.15V with 0.3V hysteresis. If OV >

6.15V, GATE pulls low. When OV returns below 5.85V,

GATE start-up begins without an initial timing cycle. If OV

occurs in the middle of an initial timing cycle, the initial

timing cycle is restarted after OV goes away. OV does not

reset the latched fault or PWRGD1 flag. The internal UVLO

at VIN always overrides OV. A 1nF to 10nF capacitor at OV

prevents transients and switching noise from affecting the

OV thresholds and prevents glitches at the GATE.

UV (Pin 12): Under-Voltage Input. The active low thresh-

old at the UV pin is set at 2.925V with 0.3V hysteresis. If

UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER

pull low. If UV rises above 3.225V, this initiates an initial

timing cycle followed by GATE start-up. The internal UVLO

at VIN always overrides UV. A low at UV resets an internal

fault latch. A 1nF to 10nF capacitor at UV prevents tran-

sients and switching noise from affecting the UV thresh-

olds and prevents glitches at the GATE pin.

TIMER (Pin 13): Timer Input. Timer is used to generate an

initial timing delay at start-up, and to delay shutdown in the

event of an output overload (circuit breaker fault). Timer

starts an initial timing cycle when the following conditions

are met: RESET is low, UV is high, OV is low, VIN clears

UVLO, TIMER pin is low, GATE pin is lower than VGATEL, SS

< 0.2V, and VSENSE-VEE < VCB. A pull-up current of 5µA

then charges CT, generating a time delay. If CT charges to

VTMRH (4V), the timing cycle terminates. TIMER quickly

pulls low and GATE is activated.

If SENSE exceeds 50mV while GATE is high, a circuit

breaker cycle begins with a 200

µA pull-up current charg-

ing CT. If DRAIN is approximately 7V during this cycle, the

timer pull-up has an additional current of 8 • IDRN. If SENSE

drops below 50mV before TIMER reaches 4V, a 5

µA pull-

down current slowly discharges the CT. In the event that CT

eventually integrates up to the VTMRH (4V) threshold, the

circuit breaker trips, GATE quickly pulls low and the

PWRGD1 pulls high. TIMER latches high with a 5

µA pull-

up source. This latched fault may be cleared by driving

RESET high until TIMER is pulled low. Other ways of

clearing the fault include pulling the VIN pin momentarily

below (VLKO – VLKH), pulling TIMER low with an external

device or pulling UV below 2.925V.

SQTIMER (Pin 14): Sequencing Timer Input. The se-

quencing timer provides a delay tSQT for the power good

sequencing. This delay is programmed by connecting an

appropriate capacitor to this pin. If the SQTIMER capacitor

is omitted, the SQTIMER pin ramps from 0V to 4V in about

300

µs.

EN3 (Pin 15): Power Good Status Output Three Enable.

This is a TTL compatible input that is used to control the

PWRGD3 output. When EN3 is driven low, PWRGD3 will

go high. When EN3 is driven high, PWRGD3 will go low

provided PWRGD2 has been active for for more than one

power good sequence delay (tSQT). EN3 can be used to

control the power good sequence. This pin is internally

pulled low by a 120

µA current source.

PWRGD3 (Pin 16): Power Good Status Output Three.

Power good sequence starts with PWRGD1 latching active

low. PWRGD3 will latch active low after EN3 goes high and

after one power good sequence delay tSQT provided by the

sequencing timer from the time PWRGD2 goes low,

whichever comes later. PWRGD3 is reset by PWRGD1

going high or EN3 going low. This pin is internally pulled

high by a 50

µA current source.

PI FU CTIO S

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