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LTC4253

4253f

OPERATIO

Interlock Conditions

A start-up sequence commences once these “interlock”

conditions are met:

1. The input voltage VIN exceeds 9.2V (UVLO).

2. The voltage at UV > 3.225V.

3. The voltage at OV < 5.85V.

4. The input voltage at RESET < 0.8V.

5. The (SENSE – VEE ) voltage < 50mV (VCB)

6. The voltage at SS is < 0.2V (20 • VOS)

7. The voltage on the TIMER capacitor ( CT ) is

< 1V (VTMRL).

8. The voltage at GATE is < 0.5V (VGATEL)

The first four conditions are continuously monitored and

the latter four are checked prior to initial timing or GATE

ramp-up. Upon exiting an OV condition, the TIMER pin

voltage requirement is inhibited. Details are described in

the Applications Information, Timing Waveforms section.

TIMER begins the start-up sequence by sourcing 5

µA into

CT. If VIN, UV or OV falls out of range or RESET asserts, the

start-up cycle stops and TIMER discharges CT to less than

1V, then waits until the aforementioned conditions are

once again met. If CT successfully charges to 4V, TIMER

pulls low and both SS and GATE pins are released. GATE

sources 50

µA (IGATE), charging the MOSFET gate and

associated capacitance. The SS voltage ramp limits VSENSE

to control the inrush current. PWRGD1 pulls active low

when GATE is within 2.8V of VIN and DRAIN is lower than

VDRNL. This sets off the power good sequence in which

PWRGD2 and then PWRGD3 is subsequently pulled low

after a delay, programmable through the SQTIMER ca-

pacitor CSQ or by external control inputs EN2 and EN3. In

this way, external loads or power modules controlled by

the three PWRGD signals are turned on in a controlled

manner without overloading the power bus.

Two modes of operation are possible during the time the

MOSFET is first turned on, depending on the values of

external components, MOSFET characteristics and nomi-

nal design current. One possibility is that the MOSFET will

turn on gradually so that the inrush into the load capaci-

tance remains a low value. The output will simply ramp to

– 48V and the LTC4253 will fully enhance the MOSFET. A

second possibility is that the load current exceeds the soft-

start current limit threshold of [VSS(t)/20 – VOS]/RS. In this

case the LTC4253 will ramp the output by sourcing soft-

start limited current into the load capacitance. If the soft-

start voltage is below 1.2V, the circuit breaker TIMER is

held low. Above 1.2V, TIMER ramps up. It is important to

set the timer delay so that, regardless of which start-up

mode is used, the TIMER ramp is less than one circuit

breaker delay time. If this condition is not met, the LTC4253

may shut down after one circuit breaker delay time.

Board Removal

When the board is withdrawn from the card cage, the

UV/OV divider is the first to lose connection. This shuts off

the MOSFET and commutates the flow of current in the

connector. When the power pins subsequently separate

there is no arcing.

Current Control

Three levels of protection handle short-circuit and over-

load conditions. Load current is monitored by SENSE and

resistor RS. There are three distinct thresholds at SENSE:

50mV for a timed circuit breaker function; 100mV for an

analog current limit loop; and 200mV for a fast, feedforward

comparator which limits peak current in the event of a

catastrophic short-circuit.

If, due to an output overload, the voltage drop across RS

exceeds 50mV, TIMER sources 200

µA into CT. CT eventu-

ally charges to a 4V threshold and the LTC4253 shuts off.

If the overload goes away before CT reaches 4V and SENSE

measures less than 50mV, CT slowly discharges (5µA). In

this way the LTC4253’s circuit breaker function responds

to low duty cycle overloads, and accounts for the fast

heating and slow cooling characteristic of the MOSFET.

Higher overloads are handled by an analog current limit

loop. If the drop across RS reaches 100mV, the current

limiting loop servos the MOSFET gate and maintains a

constant output current of 100mV/RS. In current limit

mode, VOUT (MOSFET drain-source voltage drop) typically

rises and this increases MOSFET heating. If VOUT > VDRNCL

(7V), connecting an external resistor, RD between VOUT

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