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LTC4253IGN Datasheet(PDF) 28 Page - Linear Technology

Part # LTC4253IGN
Description  -48V Hot Swap Controller with Sequencer
PDF  32 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4253IGN Datasheet(HTML) 28 Page - Linear Technology

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LTC4253
28
4253f
APPLICATIO S I FOR ATIO
(Refer to Block Diagram)
delay. Careful selection of CT, RD and MOSFET helps
prevent SOA damage in a low impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 300
µs at GATE
start-up, as shown in Figure 16a. If a soft-start capacitor,
CSS, is connected to this SS pin, the soft-start response is
modified from a linear ramp to an RC response (Equa-
tion 6), as shown in Figure 16b. This feature allows load
current to slowly ramp-up at GATE start-up. Soft-start is
initiated at time point 3 by a TIMER transition from VTMRH
to VTMRL (time points 1 and 2) or by the OV pin falling
below the VOVLO threshold after an OV condition. When the
SS pin is below 0.2V, the analog current limit amplifier
keeps GATE low. Above 0.2V, GATE is released and 50
µA
ramps up the compensation network and GATE capaci-
tance at time point 4. Meanwhile, the SS pin voltage
continues to ramp up. When GATE reaches the MOSFET’s
threshold, the MOSFET begins to conduct. Due to the
MOSFET’s high gm, the MOSFET current quickly reaches
the soft-start control value of VACL(t) (Equation 7). At time
point 6, the GATE voltage is controlled by the current limit
amplifier. The soft-start control voltage reaches the circuit
breaker voltage, VCB at time point 7 and the circuit breaker
TIMER activates. As the load capacitor nears full charge,
load current begins to decline below VACL(t). The current
limit loop shuts off and GATE releases at time point 8. At
time point 9, SENSE voltage falls below VCB and TIMER
deactivates.
RESET PULSE
WIDTH MUST FULLY
DISCHARGE TIMER
12 34
5
6 7 8 9
4253 F14
LATCHED TIMER RESET BY RESET PULLING HIGH
RESET PULLS LOW
TIMER
GATE
SENSE
RESET
SS
DRAIN
PWRGD1
VTMRH
VIH
VIL
VACL
VCB
VTMRL
VGATEL
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
5
µA
5
µA
50
µA
50
µA
5
µA
50
µA
VDRNCL
VDRNL
VIN – VGATEH
200
µA + 8 • IDRN
Figure 14. Reset of LTC4253’s Latched Fault (All Waveforms are Referenced to VEE)



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