LTC4253IGN datasheet(18/32 Pages) LINER

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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

POWER GOOD SEQUENCING

After the initial TIMER cycle, GATE ramps up to turn on the

external MOSFET which in turn pulls DRAIN low. When

GATE is within 2.8V of VIN and DRAIN is lower than VDRNL,

the power good sequence starts with PWRGD1 pulling

active low. This starts off a 5

µA pull-up on the SQTIMER

pin which ramps up until it reaches the 4V threshold then

pulls low. When the SQTIMER pin floats, this delay tSQT is

about 300

µs. Connecting an external capacitor CSQ from

SQTIMER to VEE modifies the delay to:

SQT

•

(5)

PWRGD2 asserts when EN2 goes high and PWRGD1 has

asserted for more than one tSQT. When PWRGD2 success-

fully pulls low, SQTIMER ramps up on another delay cycle.

PWRGD3 asserts when EN2 and EN3 go high and PWRGD2

has asserted for more than one tSQT.

All three PWRGD signals are reset in UVLO, in UV condi-

tion, if RESET is high or when CT charges up to 4V. In

addition, PWRGD2 is reset by EN2 going low. PWRGD3 is

reset by EN2 or EN3 going low. An overvoltage condition

has no effect on the PWRGD flags. A 50

µA current pulls

each PWRGD pin high when reset. As power modules

signal common are different from PWRGD, optoisolation

is recommended. These three pins can sink an optodiode

current.

SOFT-START

Soft-start is effective in limiting the inrush current during

GATE start-up. Unduly long soft-start intervals can exceed

the MOSFET’s SOA duration if powering-up into an active

load. When the SS pin floats, an internal current source

ramps SS from 0V to 2.2V in about 300

µs. Connecting an

external capacitor, CSS, from SS to ground modifies the

ramp to approximate an RC response of:

()

–

≈−













(6)

An internal resistor divider (95k/5k) scales VSS(t) down by

20 times to give the analog current limit threshold:

ACL

()

•

(7)

This allows the inrush current to be limited to VACL(t)/RS.

The offset voltage, VOS (10mV) ensures CSS is sufficiently

discharged and the ACL amplifier is in current limit mode

before GATE start-up. SS is discharged low during UVLO

at VIN , UV, OV, during the initial timing cycle, a latched

circuit breaker fault or the RESET pin going high.

GATE

GATE is pulled low to VEE under any of the following

conditions: in UVLO, when RESET pulls high, in an

undervoltage condition, in an overvoltage condition, dur-

ing the initial timing cycle or a latched circuit breaker fault.

When GATE turns on, a 50

µA current source charges the

MOSFET gate and any associated external capacitance.

VIN limits the gate drive to no more than 14.5V.

Gate-drain capacitance (CGD) feedthrough at the first

abrupt application of power can cause a gate-source

voltage sufficient to turn on the MOSFET. A unique circuit

pulls GATE low with practically no usable voltage at VIN,

and eliminates current spikes at insertion. A large external

gate-source capacitor is thus unnecessary for the purpose

of compensating CGD. Instead, a smaller value (≥10nF)

capacitor CC is adequate. CC also provides compensation

for the analog current limit loop.

GATE has two comparators: the GATE low comparator

looks for < 0.5V threshold prior to initial timing; the GATE

high comparator looks for < 2.8V relative to VIN and,

together with DRAIN low comparator, sets PWRGD1

output during GATE startup.

SENSE

The SENSE pin is monitored by the circuit breaker (CB)

comparator, the analog current limit (ACL) amplifier, and

the fast current limit (FCL) comparator. Each of these three

measures the potential of SENSE relative to VEE. When

SENSE exceeds 50mV, the CB comparator activates the

200

µA TIMER pull-up. At 100mV the ACL amplifier servos

the MOSFET current, and at 200mV the FCL comparator

abruptly pulls GATE low in an attempt to bring the MOSFET

current under control. If any of these conditions persists

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