LTC4253IGN datasheet(24/32 Pages) LINER

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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

GATE

START-UP

INITIAL TIMING

VUVHI

VLKO

VGATEL

VSQTMRH

VSQTMRL

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

SENSE

UV CLEARS VUVHI, CHECK OV < VOVHI, RESET = 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

VOUT

3 4 5 6

789

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

DRAIN

PWRGD1

A B

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

µA

VSQTMRH

4253 F09

VSQTMRL

VTMRH

VACL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

µA

VDRNCL

VDRNL

VIN – VGATEH

200

µA + 8 • IDRN

Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)

VIN Undervoltage Lockout Timing

VIN undervoltage lockout comparator, UVLO has a similar

timing behaviour as the UV pin timing except it looks at VIN

for (VLKO – VLKH) to shut down and VLKO to revive. In VIN

shutdown, both UV and OV comparators are preset off.

This effectively causes the UV comparator to look for

VUVHI threshold and OV comparator to look for VOVLO

threshold when VIN comes out of undervoltage lockout.

Undervoltage Timing with Overvoltage Glitch

In Figure 11, both UV and OV pins are connected together,

clears VUVHI (time point 1), an initial timing cycle starts. If

the system bus voltage overshoots VOVHI as shown at time

point 2, TIMER discharges. At time point 3, the supply

voltage recovers and drops below the VOVLO threshold.

The initial timing cycle restarts and is followed by a GATE

start-up cycle.

Overvoltage Timing

During normal operation, if the OV pin exceeds VOVHI as

shown at time point 1 of Figure 12, the TIMER and PWRGD

status are unaffected; SS and GATE pull down; load

disconnects. At time point 2, OV recovers and drops below

the VOVLO threshold; GATE start-up begins. If the overvolt-

age glitch is long enough to deplete the load capacitor,

time points 4 through 7 may occur.

LTC4253IGN Datasheet(PDF) 24 Page - Linear Technology

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