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LTC4253

4253f

ing starts and the TIMER capacitor is charged by a 5

µA

current source pull-up. At time point 3, TIMER reaches the

VTMRH threshold and the initial timing cycle terminates.

The TIMER capacitor is quickly discharged. At time point 4,

the VTMRL threshold is reached and the conditions of

GATE < VGATEL, SENSE < VCB and SS < 20 • VOS must be

satisfied before the GATE start-up cycle begins. SS ramps

up as dictated by RSS • CSS; GATE is held low by the analog

current limit amplifier until SS crosses 20 • VOS. Upon

releasing GATE, 50

µA sources into the external MOSFET

gate and compensation network. When the GATE voltage

reaches the MOSFET’s threshold, current begins flowing

into the load capacitor at time point 5. At time point 6, load

current reaches SS control level and the analog current

limit loop activates. Between time points 6 and 8, the GATE

voltage is servoed and the SENSE voltage is regulated at

VACL(t) and soft-start limits the slew rate of the load

current. If the SENSE voltage (VSENSE – VEE) reaches the

VCB threshold at time point 7, the circuit breaker TIMER

activates. The TIMER capacitor, CT is charged by a

(200

µA + 8 • IDRN) current pull-up. As the load capacitor

nears full charge, load current begins to decline. At point 8,

the load current falls and the SENSE voltage drops below

VACL(t). The analog current limit loop shuts off and the

GATE pin ramps further. At time point 9, the SENSE

voltage drops below VCB and the fault TIMER ends, fol-

lowed by a 5

µA discharge current source (cool-off). When

GATE ramps past VGATEH threshold at time point A,

PWRGD1 pulls low, starting off the PWRGD sequence.

PWRGD2 pulls low at time point C when EN2 is high and

PWRGD1 is low for more than one tSQT. PWRGD3 pulls

low at time point D when EN2 and EN3 is high and

PWRGD2 is low for more than one tSQT. At time point B,

GATE reaches its maximum voltage as determined by VIN.

Undervoltage Timing

In Figure 10 when the UV pin drops below VUVLO (time

point 1), the LTC4253 shuts down with TIMER, SS and

GATE pulled low. If current has been flowing, the SENSE

pin voltage decreases to zero as GATE collapses. When UV

recovers and clears VUVHI (time point 2), an initial time

cycle begins followed by a start-up cycle.

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

GATE, 50

µA sources into the external MOSFET gate and

compensation network. When the GATE voltage reaches

the MOSFET’s threshold, current flows into the load ca-

pacitor at time point 5. At time point 6, load current

reaches SS control level and the analog current limit loop

activates. Between time points 6 and 8, the GATE voltage

is servoed, the SENSE voltage is regulated at VACL(t)

(equation 7) and soft-start limits the slew rate of the load

current. If the SENSE voltage (VSENSE – VEE) reaches the

VCB threshold at time point 7, circuit breaker TIMER

activates. The TIMER capacitor, CT is charged by a

(200

µA + 8 • IDRN) current pull-up. As the load capacitor

nears full charge, load current begins to decline. At time

point 8, the load current falls and the SENSE voltage drops

below VACL(t). The analog current limit loop shuts off and

the GATE pin ramps further. At time point 9, the SENSE

voltage drops below VCB, the fault TIMER ends, followed

by a 5

µA discharge cycle (cool-off). The duration between

time points 7 and 9 must be shorter than one circuit

breaker delay to avoid fault time-out during GATE ramp-

up. When GATE ramps past the VGATEH threshold at time

point A, PWRGD1 pulls low. At time point B, GATE reaches

its maximum voltage as determined by VIN. At time point

A, SQTIMER starts its ramp-up to 4V. Having satisfied the

requirement that PWRGD1 is low for more than one tSQT,

PWRGD2 pulls low after EN2 pulls high above the VIH

threshold at time point C. This sets off the second SQTIMER

ramp-up. Having satisfied the requirement that PWRGD2

is low for more than one tSQT, PWRGD3 pulls low after EN3

pulls high at time point D.

Live Insertion with Short Pin Control of UV/OV

In the example shown in Figure 9, power is delivered

through long connector pins whereas the UV/OV divider

makes contact through a short pin. This ensures the power

connections are firmly established before the LTC4253 is

activated. At time point 1, the power pins make contact and

VIN ramps through VLKO. At time point 2, the UV/OV divider

makes contact and its voltage exceeds VUVHI. In addition,

the internal logic checks for OV < VOVHI, RESET < 0.8V,

GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and

TIMER < VTMRL. When all conditions are met, initial tim-

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