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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

Large values of CSS can cause premature circuit breaker

time-out as VACL(t) may marginally exceed the VCB poten-

tial during the circuit breaker delay. The load capacitor is

unable to achieve full charge in one GATE start-up cycle.

A more serious side effect of a large CSS value is that SOA

duration may be exceeded during soft-start into a low

impedance load. A soft-start voltage below VCB will not

activate the circuit breaker TIMER.

Power Limit Circuit Breaker

Figure 17 shows the LTC4253 in a power limit circuit

breaking application. The SENSE pin is modulated by

board voltage VSUPPLY. The zener voltage, VZ of D1, is set

to be the same as the lowest operating voltage,

VSUPPLY(MIN) = 36V. If the goal is to have the high supply

operating voltage, VSUPPLY(MAX) = 72V give the same

power as available at VSUPPLY(MIN), then resistors R3 and

R7 are selected by:

SUPPLY MAX

()

(16)

If R7 is 22

Ω, then R3 is 31.6k. The peak circuit breaker

power limit is:

3 4

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD1

4253 F15

CB TIMES-OUT

VTMRH

VACL

VCB

VACL

VFCL

VCB

µA

200

µA + 8 • IDRN

200

µA + 8 • IDRN

VDRNCL

VTMRH

Figure 15. Current Limit Behavior (All Waveforms are Referenced to VEE)

(15a) Analog Current Limit Fault

(15b) Fast Current Limit Fault

POWER MAX

POWER AT V

SUPPLY MIN

SUPPLY MAX

SUPPLY MIN

()

••

•

.•

()

(

)

()

1 125

(17)

when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX))

= 54V

The peak power at the fault current limit occurs at the

supply overvoltage threshold. The fault current limited

power is:

POWER FAULT

SUPPLY

ACL

SUPPLY

()

•(

)•

()

−−









(18)

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