LTC4253IGN datasheet(19/32 Pages) LINER

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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

long enough for TIMER to charge CT to 4V (see Equa-

tion 3), the LTC4253 shuts down and pulls GATE low.

If the SENSE pin encounters a voltage greater than 100mV,

the ACL amplifier will servo GATE downwards in an

attempt to control the MOSFET current. Since GATE over-

drives the MOSFET in normal operation, the ACL amplifier

needs time to discharge GATE to the threshold of the

MOSFET. For a mild overload the ACL amplifier can control

the MOSFET current, but in the event of a severe overload

the current may overshoot. At SENSE = 200mV the FCL

comparator takes over, quickly discharging the GATE pin

to near VEE potential. FCL then releases, and the ACL

amplifier takes over. All the while TIMER is running. The

effect of FCL is to add a nonlinear response to the control

loop in favor of reducing MOSFET current.

Owing to inductive effects in the system, FCL typically

overcorrects the current limit loop, and GATE under-

shoots. A zero in the loop (resistor RC in series with the

gate capacitor) helps the ACL amplifier to recover.

SHORT-CIRCUIT OPERATION

Circuit behavior arising from a load side low impedance

short is shown in Figure 5. Initially the current overshoots

the analog current limit level of VSENSE = 200mV (trace 2)

as the GATE pin works to bring VGS under control (trace 3).

The overshoot glitches the backplane in the negative

direction and when the current is reduced to 100mV/RS,

the backplane responds by glitching in the positive direc-

tion.

TIMER commences charging CT (trace 4) while the analog

current limit loop maintains the fault current at 100mV/RS,

which in this case is 5A (trace 2). Note that the backplane

voltage (trace 1) sags under load. Timer pull-up is accel-

erated by VOUT. When CT reaches 4V, GATE turns off, the

PWRGD signal pulls high, the load current drops to zero

and the backplane rings up to over 100V. The positive peak

is usually limited by avalanche breakdown in the MOSFET,

and can be further limited by adding a zener diode (such

as Diodes Inc. SMAT70A) across the input from – 48V to

– 48RTN.

A low impedance short on one card may influence the

behavior of others sharing the same backplane. The initial

glitch and backplane sag as seen in Figure 5 trace 1, can

rob charge from output capacitors on the adjacent card.

When the faulty card shuts down, current flows in to

refresh the capacitors. If LTC4253s are used by the other

cards, they respond by limiting the inrush current to a

value of 100mV/RS. If CT is sized correctly, the capacitors

will recharge long before CT times out.

MOSFET SELECTION

The external MOSFET switch must have adequate safe

operating area (SOA) to handle short-circuit conditions

until TIMER times out. These considerations take prece-

dence over DC current ratings. A MOSFET with adequate

SOA for a given application can always handle the required

current but the opposite may not be true. Consult the

manufacturer’s MOSFET datasheet for safe operating area

and effective transient thermal impedance curves.

MOSFET selection is a 3-step process by assuming the

absense of soft-start capacitor. First, RS is calculated and

then the time required to charge the load capacitance is

determined. This timing, along with the maximum short-

circuit current and maximum input voltage, defines an

operating point that is checked against the MOSFET’s SOA

curve.

To begin a design, first specify the required load current

and Ioad capacitance, IL and CL. The circuit breaker

current trip point (VCB/RS) should be set to accommodate

the maximum load current. Note that maximum input

current to a DC/DC converter is expected at VSUPPLY(MIN).

RS is given by:

GATE

0.5ms

10V

SENSE

0.5ms

200mV

–48RTN

0.5ms

50V

TIMER

0.5ms

4253 F05

SUPPLY RING OWING

TO CURRENT OVERSHOOT

SUPPLY RING OWING

TO MOSFET TURN-OFF

ONSET OF OUTPUT

SHORT-CIRCUIT

FAST CURRENT

LIMIT

CTIMER RAMP

LATCH OFF

TRACE 1

TRACE 2

TRACE 3

TRACE 4

ANALOG

CURRENT LIMIT

Figure 5. Output Short-Circuit Behavior of LTC4253

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