LTC4253IGN datasheet(22/32 Pages) LINER

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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

time point 1, the supply ramps up, together with UV/OV,

VOUT and DRAIN. VIN and the PWRGD signals follow at a

slower rate as set by the VIN bypass capacitor. At time

point 2, VIN exceeds VLKO and the internal logic checks for

UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL,

SENSE < VCB, SS < 20 • VOS, and TIMER < VTMRL. When

all conditions are met, initial timing starts and the TIMER

capacitor is charged by a 5

µA current source pull-up. At

time point 3, TIMER reaches the VTMRH threshold and the

initial timing cycle terminates. The TIMER capacitor is

quickly discharged. At time point 4, the VTMRL threshold is

reached and the conditions of GATE < VGATEL,SENSE < VCB

and SS < 20 • VOS must be satisfied before the GATE start-

up cycle begins. SS ramps up as dictated by RSS • CSS (as

in Equation 6); GATE is held low by the analog current limit

(ACL) amplifier until SS crosses 20 • VOS. Upon releasing

4253 F08

GATE

START-UP

INITIAL TIMING

VLKO

VGATEL

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

SENSE

VOUT

3 4 56

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

VSQTMRH

µA

VSQTMRH

VIH

VTMRH

VACL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

µA

VDRNCL

VDRNL

VIN – VGATEH

200

µA + 8 • IDRN

Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)

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