LTC4253IGN datasheet(25/32 Pages) LINER

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LTC4253

4253f

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)

µA

VSQTMRL

UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

TIMER

GATE

SENSE

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

3 4 56

8 9 A B

4253 F10

INITIAL TIMING

GATE

START-UP

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

µA

UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES

VUVLO

VGATEL

VUVHI

VACL

VSQTMRH

VSQTMRL

VCB

µA

VSQTMRH

VDRNCL

VDRNL

VIN – VGATEH

µA

200

µA + 8 • IDRN

VTMRH

VTMRL

µA

Circuit Breaker Timing

In Figure 13a, the TIMER capacitor charges at 200

µA if the

SENSE pin exceeds VCB but VDRN is less than 6.15V. If the

SENSE pin returns below VCB before TIMER reaches the

VTMRH threshold, TIMER is discharged by 5µA. In

Figure 13b, when TIMER exceeds VTMRH, GATE pulls

down immediately and the chip shuts down. In Figure 13c,

multiple momentary faults cause the TIMER capacitor to

integrate and reach VTMRH followed by GATE pull down

and the chip shuts down. During chip shutdown, LTC4253

latches TIMER high with a 5

µA pull-up current source.

Resetting a Fault Latch

A latched circuit breaker fault of the LTC4253 has the

benefit of a long cooling time. The latched fault can be

reset by pulsing the RESET pin high until the TIMER pin is

pulled below VTMRL( 1V ) as shown in Figure 14. After the

RESET pulse, SS and GATE ramp up without an initial

timing cycle provided the interlock conditions are satis-

fied.

Alternative methods of reset include using an external

switch to pulse the UV pin below VUVLO or the VIN pin

below (VLKO – VLKH). Pulling the TIMER pin below VTMRL

and the SS pin to 0V then simultaneously releasing them

also achieves a reset. An initial timing cycle is generated

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