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A31316 Datasheet(PDF) 40 Page - Allegro MicroSystems

Part # A31316
Description  3D Magnetic Position Sensor IC
PDF  61 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A31316 Datasheet(HTML) 40 Page - Allegro MicroSystems

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3D Magnetic Position Sensor IC
A31316
40
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
access by either customer or factory, removing available support
options from the factory.
NOTE: When any of the EEPROM lock options are set, non-
destructive factory debug support is limited.
Table 28: Serial Communication Lockout Modes
mem_lock_sel[3:0] Lock Mode
Description
4’b0011
EELOCK
EEPROM Lock: Prevents writes to
EEPROM but all volatile registers including
shadow can be written. All registers and
EEPROM can be read normally.
4’b0110
WRLOCK
Write Lock: Prevents writing anything to
either EEPROM or registers. Factory debug
support is still available
4’b1100
FLOCK
Full Lock: Prevents writing and reading to
any register in the device.
EEPROM Margin Checking
The A31316 contains a test mode, EEPROM Margining, to check
the logic levels of the EEPROM bits. The EEPROM margining
is accessible with customer access. The EEPROM margining is
selectable to check all logic 1, logic 0, or both. The results of the
test are reported back in EEPROM registers.
Note: A fail of the margin test does not force the output to a
diagnostic state.
Error Flag Registers
The different error flags available in the A31316 are stored in the
primary memory space of register 0xA4. If the error conditions
are removed, all the non-critical error flags are cleared on a read
of this register, or after being sent out through the output proto-
cols. The register contents can be seen in Table 29.
Table 29: Error Registers
Address
NAME
Access
Bit
31…13
12
11
10
9
8
7
6
5
4
3
2
1
0
0xA3
error
RO
0
OFE
SPE
EUE
OVD
UVD
ESE
POR
SRR
SLF
SAT
TSE
AOC
ACF
Analog Check Failure (ACF)
To ensure proper operation of the internal regulators, a voltage
check is done on the different reference sources for the analog and
digital circuitry, as well as for the Hall element drivers. If any of
these voltages deviate to where the accuracy of the part will be
in question, the ACF flag will be set and the device will go into a
state as defined in Table 32. If the voltages are detected to recover,
a read of the device register or reporting through the output modes
will clear the error flag so normal operation can resume. The ACF
flag can be disabled by setting acf_mask bit in EEPROM.
Angle Outside Clamp (AOC)
If the upper and lower clamps are set within the operating range
of the device, the AOC flag can be set as shown in Table 32 to
indicate the signal reaching this clamp value. If the signal moves
back within the range defined ang_clamp_high and ang_clamp_
low as described in the Output Clamps section, the AOC flag can
be removed by a read of the device register or through reporting
in the applicable output protocol. If the flag is not desired, the
EEPROM bit aoc_mask can be set. The AOC error is updated
with every angle update. However, the error may be suppressed
for up to 16 tupdate based on the fault_filt EEPROM setting.
Temperature Error (TSE)
The TSE flag is set if the temperature sensor output saturates
high, which indicates the ambient temperature is greater than
175.138°C or if the measured temperature is less than –54.963°C.
If any of these conditions occur the TSE flag will be set, and the
device will go into a state as defined in Table 32. If the tempera-
ture is detected to recover, a read of the device register or report-
ing through the output modes will clear the error flag so normal
operation can resume. The TSE flag can be disabled by setting
tse_mask bit in EEPROM. The TSE error is detected every nomi-
nal 1.5 ms and reaches the output after latest 1.62 ms.
Saturation Flag (SAT)
The Saturation Flag is provided to warn the user in case the mag-
netic signal is outside of the detectable range of the signal path. A
saturation can occur:
• In the ADC and filters, which would indicate a front-end gain
too large for the detected field, or
• A digital signal path saturation which would indicate a gain
setting too large.
If either of these conditions occur, the SAT flag will be set as
defined in Table 35. If the saturation condition is removed, the



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