83C145 datasheet(8/40 Pages) PHILIPS

8 / 40 page

1996 Mar 22

Philips Semiconductors

Product speciﬁcation

Microcontrollers for TV and video (MTV)

83C145; 83C845

83C055; 87C055

DESCRIPTION OF STANDARD FUNCTIONS

For a description of the standard functions please refer to

the

“Data Handbook IC20; Section 2: 80C51 Technical

Description” .

INPUT/OUTPUT (I/O)

The I/O structure of the 83C055 is similar to the standard

I/O structure in the 80C51, except for the points described

in Table 5.

DESCRIPTION OF DERIVATIVE FUNCTIONS

9.1

General description

Although the 83C055 is specifically referred to throughout

this data sheet, the information applies to all the devices.

The differences to 80C51 features and the derivative

functions are described in the following Sections and

Chapters.

Figure 1 shows the block diagram of the 83C055.

9.1.1

NOT IMPLEMENTED FUNCTIONS

Standard functions to the 80C51 that are not implemented

in the 83C055:

• As Data and Program Memory are not externally

expandable on the 83C055, the ALE, EA, and

PSEN signals are not implemented.

• Idle mode.

• Power-down mode.

9.1.2

INTERRUPT FACILITIES DIFFERENCES

The interrupt facilities of the 83C055 differ from those of

the 80C51 as follows:

• The IP register is not used, and the IE register (address

A8H) is similar to that on the 80C51;see Table 36.

• The VSYNC input used by the OSD facility can generate

an interrupt. The active polarity of the pulse is

programmable (see Section 13.7); interrupt occurs at

the leading edge of the pulse.

• Since there is no serial port, there are no interrupts nor

control bits relating to this interrupt. The interrupts and

their vector addresses are shown in Table 3.

• External Interrupt 1 is modified so that an interrupt is

generated when the input switches are in either direction

(on the 80C51, there is a programmable choice between

interrupt on a negative edge or a LOW level on INT1).

This facility allows for software pulse-width

measurement handling of a remote control.

Table 3

Program Memory address

9.1.3

PCON REGISTER DIFFERENCE

The PCON register format is shown in Table 4. Bits GF1

and GF0 are general purpose flag bits.

Table 4

PCON Register format (address 87H)

EVENT

PROGRAM MEMORY ADDRESS

Reset

000H

External INT0

003H

Timer 0

00BH

External INT1

013H

Timer 1

01BH

VSync Start

023H

76543210

−−−−

GF1

GF0

−−

9.1.4

I/O PORTS DIFFERENCES

Table 5

I/O ports differences

I/O

STANDARD 80C51

83C055

Port 0

external memory expansion

8-bit open-drain bidirectional port; and includes:

alternative use for PWM outputs

Port 1

8-bit general purpose quasi-bidirectional

4-bit open-drain port, and includes alternative uses

for analog inputs and a PWM output

Port 2

quasi-bidirectional and can be used for external

memory expansion

open-drain and general purpose

Port 3

quasi-bidirectional; all eight bits have alternate uses 3 port bits have some of the same alternative uses

as on the 80C51 but not necessarily on the same

pins; 5 pins are open-drain and general purpose

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