83C145 datasheet(17/40 Pages) PHILIPS

17 / 40 page

1996 Mar 22

Philips Semiconductors

Product speciﬁcation

Microcontrollers for TV and video (MTV)

83C145; 83C845

83C055; 87C055

13.1.9

SHORT ROWS

This mode only displays 4 horizontal lines and is used for

generating underlines.

13.1.10 PROGRAMMABLE HORIZONTAL AND VERTICAL

POSITIONS

Bit pairs HS4 to HS0 and VS2 to VS0 in register OSORG

(Table 30) define the starting point of the display.

13.2

General description of the OSD module

This block is the largest of the additions that are specific to

this product. Its basic function is to superimpose text on

the television video image, to indicate various parameters

and settings of the receiver or tuner. External circuitry

handles the mixing (multiplexing) of the text and the TV

video. The OSD block has 4 input pins:

• Two for a video clock: VCLK1 and VCLK2

• Horizontal sync signal: HSYNC

• Vertical sync signal: VSYNC.

The block has 4 outputs:

• 3 colour video signals

• a control signal.

Since this block is the major feature of the part, its main

inputs and outputs are dedicated pins, without alternate

port bits. The OSD of the 83C055 differs from that in

preceding devices in one major way:

• It does not fix the number and size of displayed rows of

text.

Several predecessor parts allowed two displayed rows of

16 characters each. The 83C055 simply has 128 locations

of Display RAM, each of which can contain:

• a displayed character, or

• a New Line character that indicates the end of a row.

A variant of the New Line character is used to indicate

the end of displayed data.

A number of changes in the OSD architecture have

reduced the number of other Special Function Registers

involved in the feature, below the number needed with

predecessor devices:

1. The elimination of certain options such as 4, 6, or

× character sizes and alternate use of two of the

video outputs.

2. The moving of certain other options from central

registers to Display RAM, such as foreground colour

codes (Fcolor) and background (B) selection.

Figure 7 shows the 3 major elements of the OSD facility:

• OSD logic

• Display RAM

• Character Generator ROM.

13.3

OSD logic

For a standard NTSC TV signal with an HSYNC frequency

of 15.750 kHz and a VSYNC frequency of nominally

60 Hz, there are roughly 50

µs of active horizontal scan

line available.

A typical pixel clock frequency is 8 MHz, and therefore

roughly 400 pixels of resolution can be obtained. At

14 dots per character, this means 28 character per

horizontal scan line. If the 12 dot per character display

mode is used, that means 33 character per horizontal scan

line. Allowing for edge effects, 26 characters (14 across) or

31 characters (12 across) can be displayed.

Note that VGA rates and higher can be used. The

minimum character dot size will be a function of the VGA

frequency used. For a 640

× 480 display, running at

33 kHz, the equivalent 83C055 pixel resolution is about

160 across (because of the 8 MHz clock and allowing for

overscan). This means that status and diagnostic

information can be displayed on video monitors.

13.3.1

-CHIP VIDEO OSCILLATOR

The video clock pins (VCLK1 and VCLK2) are used to

connect a LC circuit to an on-chip video oscillator that is

independent of the normal MCU clock.

The L and C values are chosen so that a video pulse, of a

duration equal to the VCLK period, will produce a

more-or-less square dot on the screen, that is, a dot having

a width approximately equal to the vertical distance

between consecutive scan lines.

The video oscillator is stopped (with VCLK2 = LOW) while:

• HSYNC (Horizontal Sync) is maintained, and

• is released to operate at the trailing edge of HSYNC.

This technique helps provide uniform horizontal

positioning of characters/dots from one scan line to the

next.

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