83C145 datasheet(27/40 Pages) PHILIPS

27 / 40 page

1996 Mar 22

Philips Semiconductors

Product speciﬁcation

Microcontrollers for TV and video (MTV)

83C145; 83C845

83C055; 87C055

14.2

Programming operation

Figures 10 and 11 show the timing diagrams for the

Program/Verify cycle. Programming operation:

1. RST should initially be held HIGH for at least

2 machine cycles. P0.1 (PROG) and P0.0 (VPP) will be

at VOH as a result of the RST operation. At this point,

these pins function as normal quasi-bidirectional I/O

ports and the programming equipment may pull these

lines LOW. However, prior to sending the 10-bit code

on the RST pin, the programming equipment should

drive these pins HIGH (VIH).

2. The RST pin may now be used as the serial data input

for the data stream which places the 87C055 in the

Programming Mode. Data bits are sampled during the

clock HIGH time and thus should only change during

the time that the clock is LOW. Following transmission

of the last data bit, the RST pin should be held LOW.

3. Next the address information for the location to be

programmed is placed on Port 2 and ASEL is used to

perform the address multiplexing, as previously

described (see Table 31; note 1).

a) At this time, Port 1 functions as an output.

b) A high voltage VPP level is then applied to the VPP

input (P0.0). This sets Port 1 as an input port.

c) The data to be programmed into the EPROM array

is then placed on Port 3. This is followed by a

series of programming pulses applied to the PROG

pin (P0.1). These pulses are created by driving

P0.1 LOW and then HIGH. This pulse is repeated

until a total of 25 programming pulses have

occurred. At the conclusion of the last pulse, the

PROG signal should remain HIGH.

4. The VPP signal may now be driven to the VOH level,

placing the 87C055 in the Verify Mode; Port 3 is now

used as an output port. After four machine cycles

(48 clock periods), the contents of the addressed

location in the EPROM array will appear on Port 3.

5. The next programming cycle may now be initiated by:

a) Placing the address information at the inputs of the

multiplexed buffers.

b) Driving the VPP pin to the VPP voltage level.

c) Providing the byte to be programmed to Port 3 and

issuing the 26 programming pulses on the PROG

pin.

d) Bringing VPP back down to the VOH level and

verifying the byte (see Table 33).

14.3

Erasure Characteristics

Erasure of the EPROM begins to occur when the chip is

exposed to light with wavelengths shorter than

approximately 4000 Angstroms. Since sunlight and

fluorescent lighting have wavelengths in this range,

exposure to these light sources over an extended time

(about 1 week in sunlight, or 3 years in room level

fluorescent lighting) could cause inadvertent erasure.

For this and secondary effects, it is recommended that an

opaque label be placed over the window. For elevated

temperature or environments where solvents are being

used, apply Kapton tape Fluorless (part number 2345-5) or

equivalent.

The recommended erasure procedure is exposure to

ultraviolet light (at 2537 Angstroms) to an integrated dose

of at least 15 Ws/cm2.

Exposing the EPROM to an ultraviolet lamp of

12000

µW/cm2 rating for 20 to 39 minutes, at a distance of

about 1 inch, should be sufficient. Erasure leaves the array

in an all logic 1s state.

14.4

Reading Signature Bytes

The Signature Bytes are read by the same procedure as a

normal verify of locations 30H and 31H (the values are

shown in Table 32), except that the serial code indicated in

Table 33 for reading signature bytes should be used.

Table 32 Programming and Veriﬁcation codes

Table 33 Implementing Program/Verify Modes

Note

1. Pulsed from VIH to VIL and returned to VIH.

ADDRESS

CONTENT

INDICATION

30H

15H

manufactured by Philips

31H

4BH

87C055

OPERATION

SERIAL

CODE

P0.1

(PROG)

P0.0

(VPP)

Program user EPROM

286H

−(1)

VPP

Verify user EPROM

286H

VIH

Read Signature Bytes

280H

VIH

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