83C145 datasheet(35/40 Pages) PHILIPS

35 / 40 page

1996 Mar 22

Philips Semiconductors

Product speciﬁcation

Microcontrollers for TV and video (MTV)

83C145; 83C845

83C055; 87C055

19 DC CHARACTERISTICS

VDD =5V ±10% Tamb = 0 to +70 °C; all voltages with respect to VSS; unless otherwise speciﬁed.

Notes

1. IDD measured with OSD block initialized and RST remaining LOW.

2. This maximum applies at all times, including during power switching, and must be accounted for in power supply

design. During a Power-on process, the +12 V source used for external pull-up resistors should not precede the VDD

of the 83C055 up their respective voltage ramps by more than this margin, nor, during a Power-down process, should

VDD precede +12 V down their respective voltage ramps by more than this margin.

3. No more than 6 (any 6) of these 10 high current outputs may be used at the VOL1 (IOL = 10 mA) specification.

The other 4 should comply with the VOL3 specification (IOL = 1.6 mA).

4. The specified current rating applies when any of these pins is used as a Pulse Width Modulated (PWM) output.

For use as a port output, the rating is as given subsequently.

5. The capacitance of pins P0.0 and P0.7 for the 87C055 exceeds 10 pF; for P0.0 this is maximum 40 pF, while for P0.7

it is maximum 20 pF.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

VDD

operating supply voltage

4.5

5.0

5.5

IDD

operating supply current

VDD = 5.5 V; note 1

−−

VIL

LOW level input voltage

−0.5

−

0.2VDD − 0.1 V

VIL1

LOW level input voltage;

VSYNC and HSYNC

−0.5

−

0.15VDD

VIH

HIGH level input voltage;

XTAL, VCLK1 and RST

0.7VDD

−

VDD + 0.5

VIH1

HIGH level input voltage; P1.2 to P1.0,

P3.6 to P3.5 and P3.3 to P3.1

0.2VDD + 0.9 −

VDD + 0.5

VIH2

HIGH level input voltage;

P1.3, P3.7,P3.4 and P3.0

0.2VDD + 0.9 −

12.6

VIH3

HIGH level input voltage; VSYNC and

HSYNC

0.67VDD

−

VDD + 0.5

VIH − VDD HIGH level input voltage with respect

to VDD; Port 0, P1.3, P3.7, P3.4 and

P3.0

note 2

0.7VDD

−

VDD + 0.5

VOL1

LOW level output voltage; P2.7 to P2.0

and P3.6 to P3.5

IOL = 10 mA; note 3

−−

0.5

VOL2

LOW level output voltage;

TDAC and PWM0 to PWM7

IOL = 700 µA; note 4

−−

0.5

VOL3

LOW level output voltage; all other

outputs

IOL = 1.6 mA

−−

0.45

VOH

HIGH level output voltage;

Port 1, VID2 to VID0, VCTRL and BF

IOH = −60 µA

2.4

−−

RRST

Reset (RST) pull-down resistor

−

300

Ω

CIO

Pin capacitance; except P0.0 and P0.7 test freq. = 1 MHz;

Tamb =25 °C; note 5

−−

HYS

Hysteresis; VSYNC and HSYNC

0.8

−−

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