1996 Mar 22

24

Philips Semiconductors

Product specification

Microcontrollers for TV and video (MTV)

83C145; 83C845

83C055; 87C055

Table 28 Shadowing modes determined by bits SHM2 to SHM0 (register OSMOD) and Sh (register OSAT)

Note

1. The mode names are based on the position of an apparent light source, ranging from the lower left (South-west)

clockwise to the lower right (South-east); see Fig.8.

13.9

OSD Control Register OSORG

Table 29 OSD Control Register OSORG (address C2H)

Table 30 Description of OSORG bits (note 1)

Notes

1. Neither the Hstart nor Vstart parameter is affected by the D line attribute that is used to display double-sized

characters.

2. Counting variations in Wc, there may be 17 to 143 VCLK clock cycles from the end of HSYNC to the start of the first

character of each row.

3. Subsequent character rows occur directly below the first, such that the last scan line of one row is directly followed

by the first scan line of the next row. Successive New Line characters (with or without the Short Row designation)

can be used to vertically separate text rows on the screen.

SHM2

SHM1

SHM0

Sh

0

0

0

1

South-west

0

0

1

1

West

0

1

0

1

North-west

0

1

1

1

North

1

0

0

1

North-east

1

0

1

1

East

1

1

0

1

South-east

1

1

1

1

Full surround

X

X

X

0

No Shadowing

76543210

HS4

HS3

HS2

HS1

HS0

VS2

VS1

VS0

BIT

SYMBOL

DESCRIPTION

7 to 3

HS4 to HS0

HStart field; defines the horizontal start position of all the on-screen character rows, as

approximately a multiple of 4 VCLK clock cycles. Active display begins after the trailing

edge of HSYNC at the position:

Where (HStart) is the decimal value of bits (HS4 to HS0); note 2.

2 to 0

VS2 to VS0

VStart field; defines the vertical start position of the first on-screen character row, as

approximately a multiple of 4 HSYNC pulses. Active display begins after the field’s time

reference point (a range of 3 to 31)at the position:

Where (VStart) is the decimal value of bits (VS2 to VS0); note 3.

HP

4

HStart

()

×

1

+

[] VCLK clock cycle

×

one single-sized character width

()

+

=

VP

4

VStart

()

×

1

–

[] HSYNC pulses

×

=