ADS1113 datasheet(8/50 Pages) TI

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6.5 Electrical Characteristics (continued)

at VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted); maximum

and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER-SUPPLY

IVDD

Supply current

Power-down

TA = 25°C

0.5

µA

Operating

TA = 25°C

150

200

300

Power dissipation

VDD = 5.0 V

0.9

VDD = 3.3 V

0.5

VDD = 2.0 V

0.3

(1)

This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of

the device. See Table 8-1 for more information.

(2)

Best-fit INL; covers 99% of full-scale.

(3)

Includes all errors from onboard PGA and voltage reference.

6.6 Timing Requirements: I2C

over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

fSCL

SCL clock frequency

0.01

0.4

0.01

3.4

MHz

tBUF

Bus free time between START and STOP

condition

600

160

tHDSTA

Hold time after repeated START condition.

After this period, the first clock is generated.

600

160

tSUSTA

Setup time for a repeated START condition

600

160

tSUSTO

Setup time for STOP condition

600

160

tHDDAT

Data hold time

tSUDAT

Data setup time

100

tLOW

Low period of the SCL clock pin

1300

160

tHIGH

High period for the SCL clock pin

600

Rise time for both SDA and SCL signals(1)

300

160

Fall time for both SDA and SCL signals(1)

300

160

(1)

For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.

6.7 Timing Diagram

SCL

SDA

LOW

HDSTA

HDDAT

BUF

SUDAT

HIGH

SUSTA

SUSTO

Figure 6-1. I2C Interface Timing

ADS1113-Q1, ADS1114-Q1, ADS1115-Q1

SBAS563E – DECEMBER 2011 – REVISED DECEMBER 2022

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