ADS1113 datasheet(22/50 Pages) TI

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8.5.1.1 I2C Address Selection

The ADS111x-Q1 have one address pin, ADDR, that configures the I2C address of the device. This pin can

be connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin,

as shown in Table 8-2. The state of address pin ADDR is sampled continuously. Use the GND, VDD and SCL

addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line

goes low to make sure the device decodes the address correctly during I2C communication.

Table 8-2. ADDR Pin Connection and Corresponding Target Address

ADDR PIN CONNECTION

TARGET ADDRESS

GND

1001000b

VDD

1001001b

SDA

1001010b

SCL

1001011b

8.5.1.2 I2C General Call

The ADS111x-Q1 respond to the I2C general call address (0000000b) if the eighth bit is 0b. The devices

acknowledge the general call address and respond to commands in the second byte. If the second byte is

00000110b (06h), the ADS111x-Q1 reset the internal registers and enter a power-down state.

8.5.1.3 I2C Speed Modes

The I2C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast

mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock

frequency of up to 3.4 MHz. The ADS111x-Q1 are fully compatible with all three modes.

No special action is required to use the ADS111x-Q1 in standard or fast mode, but high-speed mode must

be activated. To activate high-speed mode, send a special address byte of 00001xxxb following the START

condition, where xxx are bits unique to the Hs-capable controller. This byte is called the Hs controller code,

and is different from normal address bytes; the eighth bit does not indicate read/write status. The ADS111x-Q1

do not acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs controller code. Upon

receiving a controller code, the ADS111x-Q1 switch on Hs mode filters, and communicate at up to 3.4 MHz. The

ADS111x-Q1 switch out of Hs mode with the next STOP condition.

For more information on high-speed mode, consult the I2C specification.

8.5.2 Target Mode Operations

The ADS111x-Q1 act as target receivers or target transmitters. The ADS111x-Q1 cannot drive the SCL line as

target devices.

8.5.2.1 Receive Mode

In target receive mode, the first byte transmitted from the controller to the target consists of the 7-bit device

address followed by a low R/W bit. The next byte transmitted by the controller is the Address Pointer register.

The ADS111x-Q1 then acknowledge receipt of the Address Pointer register byte. The next two bytes are written

to the address given by the register address pointer bits, P[1:0]. The ADS111x-Q1 acknowledge each byte sent.

8.5.2.2 Transmit Mode

In target transmit mode, the first byte transmitted by the controller is the 7-bit target address followed by the

high R/W bit. This byte places the target into transmit mode and indicates that the ADS111x-Q1 are being

read from. The next byte transmitted by the target is the most significant byte of the register that is indicated

by the register address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the controller.

The remaining least significant byte is then sent by the target and is followed by an acknowledgment from the

controller. The controller can terminate transmission after any byte by not acknowledging or issuing a START or

STOP condition.

ADS1113-Q1, ADS1114-Q1, ADS1115-Q1

SBAS563E – DECEMBER 2011 – REVISED DECEMBER 2022

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Product Folder Links: ADS1113-Q1 ADS1114-Q1 ADS1115-Q1

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