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ADM1067ASU Datasheet(PDF) 6 Page - Analog Devices

Part # ADM1067ASU
Description  Super Sequencer with Open-Loop Margining DACs
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM1067ASU Datasheet(HTML) 6 Page - Analog Devices

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ADM1067
Rev. B | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SCL High Time, tHIGH
4
μs
SCL, SDA Rise Time, tr
1000
μs
SCL, SDA Fall Time, tf
300
μs
Data Setup Time, tSU;DAT
250
ns
Data Hold Time, tHD;DAT
5
ns
Input Low Current, IIL
1
μA
VIN = 0
SEQUENCING ENGINE TIMING
State Change Time
10
μs
1 At least one of the VH, VPn pins must be
≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested, but is supported by characterization data at initial product release.



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