ADM1067ASU datasheet(23/32 Pages) AD

23 / 32 page

ADM1067

Rev. B | Page 23 of 32

There are 256 DAC settings available. The midcode value is

located at DAC Code 0x7F, as close as possible to the middle

of the 256 code range. The full output swing of the DACs is

+302 mV (+128 codes) and −300 mV (−127 codes) around the

selected midcode voltage. The voltage range for each midcode

voltage is shown in Table 9.

Table 9. Ranges for Midcode Voltages

Midcode

Voltage (V)

Minimum Voltage

Output (V)

Maximum Voltage

Output (V)

0.6

0.300

0.902

0.8

0.500

1.102

1.0

0.700

1.302

1.25

0.950

1.552

CHOOSING THE SIZE OF THE ATTENUATION

RESISTOR

How much this DAC voltage swing affects the output voltage of

the dc-to-dc converter that is being margined is determined by

the size of the attenuation resistor, R3.

Because the voltage at the feedback pin remains constant, the

current flowing from the feedback node to GND via R2 is a

constant. In addition, the feedback node itself is high

impedance. This means that the current flowing through R1 is

the same as the current flowing through R3. Therefore, direct

relationship exists between the extra voltage drop across R1

during margining and the voltage drop across R3.

This relationship is given by the following equation:

∂VOUT =

(

VFB − VDACOUT)

where:

∂

VOUT is the change in VOUT.

VFB is the voltage at the feedback node of the dc-to-dc converter.

VDACOUT is the voltage output of the margining DAC.

This equation demonstrates that, if the user wants the output

voltage to change by ±300 mV, then R1 = R3. If the user wants the

output voltage to change by ±600 mV, then R1 = 2 × R3, and so on.

It is best to use the full DAC output range to margin a supply.

Choosing the attenuation resistor in this way provides the most

resolution from the DAC. In other words, with one DAC code

change, the smallest effect on the dc-to-dc output voltage is

induced. If the resistor is sized up to use a code such as 27(dec)

to 227(dec) to move the dc-to-dc output by ±5%, then it takes

100 codes to move 5% (each code moves the output by 0.05%).

This is beyond the readback accuracy of the ADC, but should

not prevent the user from building a circuit to use the most

resolution.

DAC LIMITING/OTHER SAFETY FEATURES

Limit registers (called DPLIMn and DNLIMn) on the device

offer the user some protection from firmware bugs, which can

cause catastrophic board problems by forcing supplies beyond

their allowable output ranges. Essentially, the DAC code written

into the DACn register is clipped such that the code used to set

the DAC voltage is actually given by

DAC Code

= DACn, DACn ≥ DNLIMn and DACn ≤ DPLIMn

= DNLIMn,

DACn < DNLIMn

= DPLIMn,

DACn > DPLIMn

In addition, the DAC output buffer is three-stated, if DNLIMn

> DPLIMn. By programming the limit registers in this way, the

user can make it very difficult for the DAC output buffers to be

turned on at all during normal system operation (these are

among the registers downloaded from EEPROM at startup).

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