ADM1067

Rev. B | Page 7 of 32

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NC = NO CONNECT

ADM1067

TOP VIEW

(Not to Scale)

40

39

38

37

36

35

34

33

32

31

11

12

13

14

15

16

17

18

19

20

PDO1

30

PDO2

29

PDO3

28

PDO4

27

PDO5

26

PDO6

25

PDO7

24

PDO8

23

PDO9

22

PDO10

21

PIN 1

INDICATOR

Figure 3. LFCSP Pin Configuration

NC = NO CONNECT

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

NC

36

PDO1

35

PDO2

34

PDO3

33

PDO4

32

PDO5

31

PDO6

30

PDO7

29

PDO8

28

PDO9

27

PDO10

26

NC

25

ADM1067

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 4. TQFP Pin Configuration

Table 2. Pin Function Descriptions

Pin Number

LFCSP1

TQFP

Mnemonic

Description

13

1, 12, 13, 16,

24, 25, 36,

37, 48

NC

No Connection.

1 to 5

2 to 6

VX1 to VX5

(VXn)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9

7 to 10

VP1 to VP4

(VPn)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input

attenuation on a potential divider connected to these pins, the output of which connects to a

supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V

to 1.375 V.

10

11

VH

High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input

attenuation on a potential divider connected to this pin, the output of which connects to a supply

fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.

11

14

AGND2

Ground Return for Input Attenuators.

12

15

REFGND2

Ground Return for On-Chip Reference Circuits.

14

17

REFOUT

2.048 V Reference Output. Note that the capacitor must be connected between this pin and

REFGND. A 10 μF capacitor is recommended for this purpose.

15 to 20

18 to 23

DAC1 to

DAC6

Voltage Output DACs. These pins default to high impedance at power-up.

21 to 30

26 to 35

PDO10 to

PDO1

Programmable Output Drivers.

31

38

PDOGND2

Ground Return for Output Drivers.

32

39

VCCP

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin

and GND. A 10 μF capacitor is recommended for this purpose.

33

40

A0

Logic Input. This pin sets the seventh bit of the SMBus interface address.

34

41

A1

Logic Input. This pin sets the sixth bit of the SMBus interface address.

35

42

SCL

SMBus Clock Pin. Open-drain output requires external resistive pull-up.

36

43

SDA

SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.

37

44

MUP

Digital Input. Forces DACs to their lowest value, causing the voltage at the feedback node to drop.

This is compensated for by an increase in the supply output voltage, thus margining up.