ADM1067ASU datasheet(22/32 Pages) AD

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ADM1067

Rev. B | Page 22 of 32

SUPPLY MARGINING

OVERVIEW

It is often necessary for the system designer to adjust supplies,

either to optimize their level or force them away from nominal

values to characterize the system performance under these

conditions. This is a function typically performed during an in-

circuit test (ICT), such as when the manufacturer wants to

guarantee that the product under test functions correctly at

nominal supplies minus 10%.

OPEN-LOOP MARGINING

The simplest method of margining a supply is to implement an

open-loop technique. A popular method for this is to switch extra

resistors into the feedback node of a power module, such as a

dc-to-dc converter or low dropout regulator (LDO). The extra

resistor alters the voltage at the feedback or trim node and forces

the output voltage to margin up or down by a certain amount.

The ADM1067 can perform open-loop margining for up to six

supplies. The six on-board voltage DACs (DAC1 to DAC6) can

drive into the feedback pins of the power modules to be

margined. The simplest circuit to implement this function is an

attenuation resistor that connects the DACn pin to the feedback

node of a dc-to-dc converter. When the DACn output voltage is

set equal to the feedback voltage, no current flows into the

attenuation resistor, and the dc-to-dc output voltage does not

change. Taking DACn above the feedback voltage forces current

into the feedback node, and the output of the dc-to-dc

converter is forced to fall to compensate for this. The dc-to-dc

output can be forced high by setting the DACn output voltage

lower than the feedback node voltage. The series resistor can be

split in two, and the node between them decoupled with a

capacitor to ground. This can help to decouple any noise picked

up from the board. Decoupling to a ground local to the dc-to-

dc converter is recommended.

OUTPUT

DC/DC

CONVERTER

FEEDBACK

GND

ATTENUATION

RESISTOR

PCB

TRACE NOISE

DECOUPLING

CAPACITOR

ADM1067

DACOUTn

VOUT

DAC

μCONTROLLER

VIN

DEVICE

CONTROLLER

(SMBus)

Figure 27. Open-Loop Margining System Using the ADM1067

The ADM1067 can be commanded to margin a supply up or

down over the SMBus by updating the values on the relevant

DAC output.

To implement open-loop margining:

Disable the six DAC outputs.

Set the DAC output voltage equal to the voltage on the

feedback node.

Enable the DAC.

Assert MUP (drive logic high). The DAC voltage moves

down to the value set in the DNLIM register (see the

AN-698 Application Note). The output of the dc-to-dc

converter rises to compensate for this, that is, margin up.

Assert MDN (drive logic high). The DAC voltage moves down

to the value set in the DPLIM register (see the AN-698

Application Note). The output of the dc-to-dc converter

drops to compensate for this, that is, margin down.

Steps 1 to 3 ensure that when the DACn output buffer is turned

on, it has little effect on the dc-to-dc output. The DAC output

buffer is designed to power up without glitching. It does this by

first powering up the buffer to follow the pin voltage and does

not drive out onto the pin at this time. Once the output buffer is

properly enabled, the buffer input is switched over to the DAC,

and the output stage of the buffer is turned on. Output glitching

is negligible.

The margining method above assumes that margin up and mar-

gin down DAC limits have been preloaded into the ADM1067

and that only one margin up and margin down level are required.

Alternatively, a DACn output level can be dynamically altered

by an SMBus write to that DACn output register.

WRITING TO THE DACs

Four DAC ranges are offered. They can be placed with midcode

(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are

placed to correspond to the most common feedback voltages.

Centering the DAC outputs in this way provides the best use of

the DAC resolution. For most supplies, it is possible to place the

DAC midcode at the point where the dc-to-dc output is not

modified, thereby giving half of the DAC range to margin up

and the other half to margin down.

The DAC output voltage is set by the code written to the DACn

in this register. Code 0x7F is placed at the midcode voltage, as

described previously.

The output voltage is given by the following equation:

DAC Output = (DACn − 0x7F)/255 × 0.6015 + VOFF

where VOFF is one of the four offset voltages.

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