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ADM1067ASU Datasheet(PDF) 3 Page - Analog Devices

Part # ADM1067ASU
Description  Super Sequencer with Open-Loop Margining DACs
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM1067ASU Datasheet(HTML) 3 Page - Analog Devices

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ADM1067
Rev. B | Page 3 of 32
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining capability can be used for
in-circuit testing of a board during production (for example, to
verify the board functionality at −5% of nominal supplies). It
can also be used dynamically to accurately control the output
voltage of a dc-to-dc converter.
The device provides up to 10 programmable inputs for
monitoring under, over, or out-of-window faults on up to 10
supplies. In addition, 10 programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET that can be placed in
the path of a supply.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
OSC
EEPROM
SDA SCL A1
A0
SMBus
INTERFACE
DEVICE
CONTROLLER
REFOUT
10µF
REFGND
VREF
ADM1067
CONFIGURABLE
O/P DRIVER
(HV)
PDO1
PDO2
PDOGND
GND
PDO3
CONFIGURABLE
O/P DRIVER
(HV)
PDO4
CONFIGURABLE
O/P DRIVER
(LV)
PDO5
PDO6
PDO7
PDO8
PDO9
CONFIGURABLE
O/P DRIVER
(LV)
PDO10
SEQUENCING
ENGINE
VX2
VX3
VX4
VP2
VP3
VP4
VH
VP1
VX1
AGND
VX5
VDDCAP
VDD
ARBITRATOR
VCCP
REG 5.25V
CHARGE PUMP
10µF
10µF
DAC1
VOUT
DAC
DAC2
VOUT
DAC
DAC3
VOUT
DAC
DAC4
VOUT
DAC
DAC5
VOUT
DAC
DAC6
VOUT
DAC
MDN
MUP
Figure 2. Detailed Block Diagram



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