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ADM1067ASU Datasheet(PDF) 13 Page - Analog Devices

Part # ADM1067ASU
Description  Super Sequencer with Open-Loop Margining DACs
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADM1067ASU Datasheet(HTML) 13 Page - Analog Devices

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ADM1067
Rev. B | Page 13 of 32
POWERING THE ADM1067
The ADM1067 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy,
because the device is not dependent on any particular voltage
rail to keep it operational. The same pins are used for supply
fault detection (discussed in the Supply Supervision section). A
VDD arbitrator on the device chooses which supply to use. The
arbitrator can be considered an OR’ing of five LDOs together. A
supply comparator chooses the highest input to provide the on-
chip supply. There is minimal switching loss with this
architecture (~0.2 V), resulting in the ability to power the
ADM1067 from a supply as low as 3.0 V. Note that the supply
on the VXn pins cannot be used to power the device.
An external capacitor to GND is required to decouple the on-
chip supply from noise. This capacitor should be connected to
the VDDCAP pin, as shown in Figure 18. The capacitor has
another use during brownouts (momentary loss of power).
Under these conditions, when the input supply (VPn or VH)
dips transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD capacitor can then act as a reservoir to keep the device
active until the next highest supply takes over the powering of
the device. A 10 μF capacitor is recommended for this
reservoir/decoupling function.
Note that when two or more supplies are within 100 mV of each
other, the supply that first takes control of VDD keeps control.
For example, if VP1 is connected to a 3.3 V supply, VDD powers
up to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device, unless VP2
goes 100 mV higher than VP1.
SUPPLY
COMPARATOR
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
VH
VP4
VP3
VP2
VP1
VDDCAP
INTERNAL
DEVICE
SUPPLY
Figure 18. VDD Arbitrator Operation



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