LXT6155LE datasheet(19/50 Pages) INTEL

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Datasheet

155 Mbps SDH/SONET/ATM Transceiver — LXT6155

(LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RSOCLK P/N is switched to the Tx

serial clock. Also the serial output data is forced to all zeros. This feature can be disabled in SW

mode (HWSEL = High) via register #10, bit #7.

2.3.3

Crystal Reference Clock (XTALIN/XTALOUT)

An optional 19.44 MHz crystal can be connected across the XTALIN and XTALOUT pins. This

crystal reference provides an onchip clock that is independent of the external system clock

(TSICLKP/TSICLKN or TPICLK). The main functions of the crystal reference clock are threefold:

(1) to center the receive PLL at 155 MHz, (2) to keep the PLL centered at 155 MHz when LOS

asserts, and (3) In the event incoming data is lost, to provide a reference clock for other devices

which require it. The designer has the option to use this crystal reference clock or the transmit input

clock (TSICLKP/TSICLKN or TPICLK) to center the receive PLL.

2.4

Jitter

The Bellcore GR-253 standard defines jitter as the “short-term variations of a digital signal’s

significant instants from their ideal positions in time”. Significant instants are the optimum data

sampling instants. Jitter parameters can be measured at the line interface, with system interface in

loopback mode, yielding jitter accumulated in both transmitter and receiver. Isolated jitter

measurements for transmitter and receiver can also be performed. Jitter specs are divided into three

categories: jitter tolerance, jitter generation, and jitter transfer. Jitter values, in effect, measure the

performance of the receive PLL and the transmit synthesizer PLL.

2.4.1

Jitter Tolerance

Jitter tolerance is the peak-to-peak amplitude of sinusoidal jitter applied at the line interface input

that causes an equivalent 1 dB SNR loss measured as BER = 10

-10. Refer to Figure 26onpage

page 44 for the LXT6155 performance.

2.4.2

Jitter Generation (Intrinsic Jitter)

Jitter generation is the amount of transmit jitter at the output of the equipment with a jitter-free

transmit input data and clock. For SONET/SDH, jitter generation is less than 0.01 UI rms,

measured with a band-pass filter from 12 kHz to 1.3 MHz. Refer to 27 on page 45 for the LXT6155

performance.

2.4.3

Jitter Transfer

Jitter transfer is defined as the ratio of output jitter to input jitter amplitude versus jitter frequency

for a given bit rate. Input jitter amplitude is shown in the Jitter Tolerance curve. Output jitter is

under the Jitter Transfer template. Refer to Figures 27 and 28 on pages and for the LXT6155

performance.

2.5

Operational Modes

The LXT6155 functions in both Hardware standalone and Software modes. The operating mode is

set by the state of the HWSEL pin.

LXT6155LE Datasheet(PDF) 19 Page - Intel Corporation

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