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LXT6155LE Datasheet(PDF) 29 Page - Intel Corporation |
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LXT6155LE Datasheet(HTML) 29 Page - Intel Corporation |
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29 / 50 page ![]() Datasheet 29 155 Mbps SDH/SONET/ATM Transceiver — LXT6155 3:2 0.0 agc_adapt_gain AGC adaption step size: 00 = 1 01 = 2 10 = 4 11 = 8 1 1 afe_ena Analog front end enable (also enables matching filter oscillator core): 0 = disabled (no bias) 1 = enabled 00 Table 13. Equalizer & AGC, Register #5 (Address A<3:0>=0101) (Continued) Bit Default Mnemonic Description Table 14. Matching Filter 2, Register #6 (Address A<3:0>=0110) Bit Default Mnemonic Description 7:5 0.1.0 Not for customer use 4:3 1.0 Not for customer use 2:1 0.0 Not for customer use 0 1 Not for customer use 1. This register is used in CMI (co-ax) mode only. Table 15. Slicer, Register #7 (Address A<3:0>=0111) Bit Default Mnemonic Description 7:4 0.0.0.0 Not for customer use 31 - Unused 2 0 Not for customer use 1 0 Not for customer use 0 0 Not for customer use Table 16. RxPLL 1, Register #8 (Address A<3:0>=1000) Bit Default Mnemonic Description 7:5 0.1.1 Not for customer use 4:3 0.0 Not for customer use 2 0 Not for customer use 1 0 Unused 0 1 Not for customer use |
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