Electronic Components Datasheet Search
  English  ▼

X  

LXT6155LE Datasheet(PDF) 41 Page - Intel Corporation

Part # LXT6155LE
Description  155 Mbps SDH/SONET/ATM Transceiver
PDF  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT6155LE Datasheet(HTML) 41 Page - Intel Corporation

Back Button LXT6155LE Datasheet HTML 37Page - Intel Corporation LXT6155LE Datasheet HTML 38Page - Intel Corporation LXT6155LE Datasheet HTML 39Page - Intel Corporation LXT6155LE Datasheet HTML 40Page - Intel Corporation LXT6155LE Datasheet HTML 41Page - Intel Corporation LXT6155LE Datasheet HTML 42Page - Intel Corporation LXT6155LE Datasheet HTML 43Page - Intel Corporation LXT6155LE Datasheet HTML 44Page - Intel Corporation LXT6155LE Datasheet HTML 45Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 50 page
background image
Datasheet
41
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
LOS Thresholds - Coax
Assert
18
dB
Attenuation measured at 78
MHz, CMI, 75
load. 12.7 dB
cable loss plus remaining flat
loss.
De-assert
17
dB
LOS hysteresis - coax
HYS
1.0
4.0
dB
Measured from the level where
LOS is asserted. PRBS(23)
data.
Receive jitter generation2
(intrinsic jitter SONET spec)
12 kHz - 1.3 MHz
0.01
UIrms
CMI encoded PRBS(23) at
RTIP/RRING with no data jitter.
Transmit input = all zeros Refer
to Figure 27 and Table 33.
0.1
UIpp
Receive jitter generation2
(intrinsic jitter SDH spec)
500 Hz - 1.3 MHz
1.5
UIpp
65 kHz - 1.3 MHz
0.075
UIpp
Receive jitter transfer peaking
2
DC - 230 kHz
0.4
dB
PRBS(23) Data. Input jitter as
the max. tolerance curve
shown inFigure26.
Receive jitter tolerance2
0.1 Hz - 19.3 Hz
39
UIpp
BER=1E-10. Tolerated jitter
meets Figure 26
500Hz- 6.5kHz
1.5
UIpp
65 kHz -
0.15
UIpp
PLL nominal center frequency
Fnom
155.52
MHz
PLL capture range
Fcap
-20
+20
ppm
PLL track range
Ftrack
-20
+20
ppm
PLL lock time
Tlock
100
µs
PRBS(23) pattern, from data
applied at RTIP/RRING. Device
in fiber optic mode.
Equalizer adaptation time
500
bits
From data applied
Line input impedance
(RTIP and RRING)
RIN
4
k
Differential resistance
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions1
Rise/Fall time - All TTL outputs
tRF
25
ns
Load 1.6mA, 50pF
SDI to SCLK setup time
tDC
5
ns
SCLK to SDI hold time
tCDH
5
ns
SCLK low time
tCL
120
ns
SCLK high time
tCH
120
ns
SCLK rise and fall time
tR, tF
25
ns
CS to SCLK setup time
tCC
5
ns
SCLK to CS hold time
tCCH
5
ns
CS inactive time
tCWH
5
ns
SCLK to SDO valid
tCDV
0
20
ns
1. Typical values are at 25C and 3.3V. They are for design aid only; not guaranteed and not subject to production testing.
Table 31. Receive Analog Characteristics (Continued)
Parameter
Note
Min
Typ1
Max
Unit
Test Conditions
1. Typical values are at 25C and 3.3V. They are for design aid only; not guaranteed and not subject to production testing.
2. Not production tested, guaranteed by design and other correlation factors.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com